i2c.vo

IIc总线的源代码（vhdl语言）

	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\reset~combout ),
	.regout(),
	.ddioregout(),
	.padio(reset));
// synopsys translate_off
defparam \reset~I .operation_mode = "input";
defparam \reset~I .ddio_mode = "none";
defparam \reset~I .input_register_mode = "none";
defparam \reset~I .output_register_mode = "none";
defparam \reset~I .oe_register_mode = "none";
defparam \reset~I .input_async_reset = "none";
defparam \reset~I .output_async_reset = "none";
defparam \reset~I .oe_async_reset = "none";
defparam \reset~I .input_sync_reset = "none";
defparam \reset~I .output_sync_reset = "none";
defparam \reset~I .oe_sync_reset = "none";
defparam \reset~I .input_power_up = "low";
defparam \reset~I .output_power_up = "low";
defparam \reset~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_P6
stratix_io \addr_bus[12]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[12]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[12]));
// synopsys translate_off
defparam \addr_bus[12]~I .operation_mode = "input";
defparam \addr_bus[12]~I .ddio_mode = "none";
defparam \addr_bus[12]~I .input_register_mode = "none";
defparam \addr_bus[12]~I .output_register_mode = "none";
defparam \addr_bus[12]~I .oe_register_mode = "none";
defparam \addr_bus[12]~I .input_async_reset = "none";
defparam \addr_bus[12]~I .output_async_reset = "none";
defparam \addr_bus[12]~I .oe_async_reset = "none";
defparam \addr_bus[12]~I .input_sync_reset = "none";
defparam \addr_bus[12]~I .output_sync_reset = "none";
defparam \addr_bus[12]~I .oe_sync_reset = "none";
defparam \addr_bus[12]~I .input_power_up = "low";
defparam \addr_bus[12]~I .output_power_up = "low";
defparam \addr_bus[12]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_F3
stratix_io \addr_bus[15]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[15]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[15]));
// synopsys translate_off
defparam \addr_bus[15]~I .operation_mode = "input";
defparam \addr_bus[15]~I .ddio_mode = "none";
defparam \addr_bus[15]~I .input_register_mode = "none";
defparam \addr_bus[15]~I .output_register_mode = "none";
defparam \addr_bus[15]~I .oe_register_mode = "none";
defparam \addr_bus[15]~I .input_async_reset = "none";
defparam \addr_bus[15]~I .output_async_reset = "none";
defparam \addr_bus[15]~I .oe_async_reset = "none";
defparam \addr_bus[15]~I .input_sync_reset = "none";
defparam \addr_bus[15]~I .output_sync_reset = "none";
defparam \addr_bus[15]~I .oe_sync_reset = "none";
defparam \addr_bus[15]~I .input_power_up = "low";
defparam \addr_bus[15]~I .output_power_up = "low";
defparam \addr_bus[15]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_H7
stratix_io \addr_bus[16]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[16]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[16]));
// synopsys translate_off
defparam \addr_bus[16]~I .operation_mode = "input";
defparam \addr_bus[16]~I .ddio_mode = "none";
defparam \addr_bus[16]~I .input_register_mode = "none";
defparam \addr_bus[16]~I .output_register_mode = "none";
defparam \addr_bus[16]~I .oe_register_mode = "none";
defparam \addr_bus[16]~I .input_async_reset = "none";
defparam \addr_bus[16]~I .output_async_reset = "none";
defparam \addr_bus[16]~I .oe_async_reset = "none";
defparam \addr_bus[16]~I .input_sync_reset = "none";
defparam \addr_bus[16]~I .output_sync_reset = "none";
defparam \addr_bus[16]~I .oe_sync_reset = "none";
defparam \addr_bus[16]~I .input_power_up = "low";
defparam \addr_bus[16]~I .output_power_up = "low";
defparam \addr_bus[16]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_F4
stratix_io \addr_bus[21]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[21]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[21]));
// synopsys translate_off
defparam \addr_bus[21]~I .operation_mode = "input";
defparam \addr_bus[21]~I .ddio_mode = "none";
defparam \addr_bus[21]~I .input_register_mode = "none";
defparam \addr_bus[21]~I .output_register_mode = "none";
defparam \addr_bus[21]~I .oe_register_mode = "none";
defparam \addr_bus[21]~I .input_async_reset = "none";
defparam \addr_bus[21]~I .output_async_reset = "none";
defparam \addr_bus[21]~I .oe_async_reset = "none";
defparam \addr_bus[21]~I .input_sync_reset = "none";
defparam \addr_bus[21]~I .output_sync_reset = "none";
defparam \addr_bus[21]~I .oe_sync_reset = "none";
defparam \addr_bus[21]~I .input_power_up = "low";
defparam \addr_bus[21]~I .output_power_up = "low";
defparam \addr_bus[21]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_H8
stratix_io \addr_bus[8]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[8]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[8]));
// synopsys translate_off
defparam \addr_bus[8]~I .operation_mode = "input";
defparam \addr_bus[8]~I .ddio_mode = "none";
defparam \addr_bus[8]~I .input_register_mode = "none";
defparam \addr_bus[8]~I .output_register_mode = "none";
defparam \addr_bus[8]~I .oe_register_mode = "none";
defparam \addr_bus[8]~I .input_async_reset = "none";
defparam \addr_bus[8]~I .output_async_reset = "none";
defparam \addr_bus[8]~I .oe_async_reset = "none";
defparam \addr_bus[8]~I .input_sync_reset = "none";
defparam \addr_bus[8]~I .output_sync_reset = "none";
defparam \addr_bus[8]~I .oe_sync_reset = "none";
defparam \addr_bus[8]~I .input_power_up = "low";
defparam \addr_bus[8]~I .output_power_up = "low";
defparam \addr_bus[8]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X95_Y55_N2
stratix_lcell \uC_CTRL|i~3187_I (
// Equation(s):
// \uC_CTRL|i~3187  = !\addr_bus[15]~combout  & !\addr_bus[16]~combout  & !\addr_bus[21]~combout  & !\addr_bus[8]~combout 

	.clk(),
	.dataa(\addr_bus[15]~combout ),
	.datab(\addr_bus[16]~combout ),
	.datac(\addr_bus[21]~combout ),
	.datad(\addr_bus[8]~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\uC_CTRL|i~3187 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \uC_CTRL|i~3187_I .operation_mode = "normal";
defparam \uC_CTRL|i~3187_I .synch_mode = "off";
defparam \uC_CTRL|i~3187_I .register_cascade_mode = "off";
defparam \uC_CTRL|i~3187_I .sum_lutc_input = "datac";
defparam \uC_CTRL|i~3187_I .lut_mask = "0001";
defparam \uC_CTRL|i~3187_I .output_mode = "comb_only";
// synopsys translate_on

// atom is at Pin_H6
stratix_io \addr_bus[22]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[22]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[22]));
// synopsys translate_off
defparam \addr_bus[22]~I .operation_mode = "input";
defparam \addr_bus[22]~I .ddio_mode = "none";
defparam \addr_bus[22]~I .input_register_mode = "none";
defparam \addr_bus[22]~I .output_register_mode = "none";
defparam \addr_bus[22]~I .oe_register_mode = "none";
defparam \addr_bus[22]~I .input_async_reset = "none";
defparam \addr_bus[22]~I .output_async_reset = "none";
defparam \addr_bus[22]~I .oe_async_reset = "none";
defparam \addr_bus[22]~I .input_sync_reset = "none";
defparam \addr_bus[22]~I .output_sync_reset = "none";
defparam \addr_bus[22]~I .oe_sync_reset = "none";
defparam \addr_bus[22]~I .input_power_up = "low";
defparam \addr_bus[22]~I .output_power_up = "low";
defparam \addr_bus[22]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_H5
stratix_io \addr_bus[11]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[11]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[11]));
// synopsys translate_off
defparam \addr_bus[11]~I .operation_mode = "input";
defparam \addr_bus[11]~I .ddio_mode = "none";
defparam \addr_bus[11]~I .input_register_mode = "none";
defparam \addr_bus[11]~I .output_register_mode = "none";
defparam \addr_bus[11]~I .oe_register_mode = "none";
defparam \addr_bus[11]~I .input_async_reset = "none";
defparam \addr_bus[11]~I .output_async_reset = "none";
defparam \addr_bus[11]~I .oe_async_reset = "none";
defparam \addr_bus[11]~I .input_sync_reset = "none";
defparam \addr_bus[11]~I .output_sync_reset = "none";
defparam \addr_bus[11]~I .oe_sync_reset = "none";
defparam \addr_bus[11]~I .input_power_up = "low";
defparam \addr_bus[11]~I .output_power_up = "low";
defparam \addr_bus[11]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_G4
stratix_io \addr_bus[20]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[20]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[20]));
// synopsys translate_off
defparam \addr_bus[20]~I .operation_mode = "input";
defparam \addr_bus[20]~I .ddio_mode = "none";
defparam \addr_bus[20]~I .input_register_mode = "none";
defparam \addr_bus[20]~I .output_register_mode = "none";
defparam \addr_bus[20]~I .oe_register_mode = "none";
defparam \addr_bus[20]~I .input_async_reset = "none";
defparam \addr_bus[20]~I .output_async_reset = "none";
defparam \addr_bus[20]~I .oe_async_reset = "none";
defparam \addr_bus[20]~I .input_sync_reset = "none";
defparam \addr_bus[20]~I .output_sync_reset = "none";
defparam \addr_bus[20]~I .oe_sync_reset = "none";
defparam \addr_bus[20]~I .input_power_up = "low";
defparam \addr_bus[20]~I .output_power_up = "low";
defparam \addr_bus[20]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_G3
stratix_io \addr_bus[23]~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[23]~combout ),
	.regout(),
	.ddioregout(),
	.padio(addr_bus[23]));
// synopsys translate_off
defparam \addr_bus[23]~I .operation_mode = "input";
defparam \addr_bus[23]~I .ddio_mode = "none";
defparam \addr_bus[23]~I .input_register_mode = "none";
defparam \addr_bus[23]~I .output_register_mode = "none";
defparam \addr_bus[23]~I .oe_register_mode = "none";
defparam \addr_bus[23]~I .input_async_reset = "none";
defparam \addr_bus[23]~I .output_async_reset = "none";
defparam \addr_bus[23]~I .oe_async_reset = "none";
defparam \addr_bus[23]~I .input_sync_reset = "none";
defparam \addr_bus[23]~I .output_sync_reset = "none";
defparam \addr_bus[23]~I .oe_sync_reset = "none";
defparam \addr_bus[23]~I .input_power_up = "low";
defparam \addr_bus[23]~I .output_power_up = "low";
defparam \addr_bus[23]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at LC_X95_Y54_N2
stratix_lcell \uC_CTRL|i~3218_I (
// Equation(s):
// \uC_CTRL|i~3218  = !\addr_bus[20]~combout  & !\addr_bus[23]~combout 

	.clk(),
	.dataa(vcc),
	.datab(vcc),
	.datac(\addr_bus[20]~combout ),
	.datad(\addr_bus[23]~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\uC_CTRL|i~3218 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \uC_CTRL|i~3218_I .operation_mode = "normal";
defparam \uC_CTRL|i~3218_I .synch_mode = "off";
defparam \uC_CTRL|i~3218_I .register_cascade_mode = "off";
defparam \uC_CTRL|i~3218_I .sum_lutc_input = "datac";
defparam \uC_CTRL|i~3218_I .lut_mask = "000F";
defparam \uC_CTRL|i~3218_I .output_mode = "comb_only";
// synopsys translate_on