i2c.vo

IIc总线的源代码（vhdl语言）

	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\sda~0 ),
	.regout(),
	.ddioregout(),
	.padio(sda));
// synopsys translate_off
defparam \sda~I .operation_mode = "bidir";
defparam \sda~I .ddio_mode = "none";
defparam \sda~I .input_register_mode = "none";
defparam \sda~I .output_register_mode = "none";
defparam \sda~I .oe_register_mode = "none";
defparam \sda~I .input_async_reset = "none";
defparam \sda~I .output_async_reset = "none";
defparam \sda~I .oe_async_reset = "none";
defparam \sda~I .input_sync_reset = "none";
defparam \sda~I .output_sync_reset = "none";
defparam \sda~I .oe_sync_reset = "none";
defparam \sda~I .input_power_up = "low";
defparam \sda~I .output_power_up = "low";
defparam \sda~I .oe_power_up = "low";
defparam \sda~I .open_drain_output = "true";
// synopsys translate_on

// atom is at Pin_R30
stratix_io \scl~I (
	.datain(!\I2C_CTRL|scl_out_reg ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\scl~0 ),
	.regout(),
	.ddioregout(),
	.padio(scl));
// synopsys translate_off
defparam \scl~I .operation_mode = "bidir";
defparam \scl~I .ddio_mode = "none";
defparam \scl~I .input_register_mode = "none";
defparam \scl~I .output_register_mode = "none";
defparam \scl~I .oe_register_mode = "none";
defparam \scl~I .input_async_reset = "none";
defparam \scl~I .output_async_reset = "none";
defparam \scl~I .oe_async_reset = "none";
defparam \scl~I .input_sync_reset = "none";
defparam \scl~I .output_sync_reset = "none";
defparam \scl~I .oe_sync_reset = "none";
defparam \scl~I .input_power_up = "low";
defparam \scl~I .output_power_up = "low";
defparam \scl~I .oe_power_up = "low";
defparam \scl~I .open_drain_output = "true";
// synopsys translate_on

// atom is at Pin_L1
stratix_io \data_bus[7]~I (
	.datain(\uC_CTRL|data_out[7] ),
	.ddiodatain(),
	.oe(\uC_CTRL|i~3 ),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_bus[7]~0 ),
	.regout(),
	.ddioregout(),
	.padio(data_bus[7]));
// synopsys translate_off
defparam \data_bus[7]~I .operation_mode = "bidir";
defparam \data_bus[7]~I .ddio_mode = "none";
defparam \data_bus[7]~I .input_register_mode = "none";
defparam \data_bus[7]~I .output_register_mode = "none";
defparam \data_bus[7]~I .oe_register_mode = "none";
defparam \data_bus[7]~I .input_async_reset = "none";
defparam \data_bus[7]~I .output_async_reset = "none";
defparam \data_bus[7]~I .oe_async_reset = "none";
defparam \data_bus[7]~I .input_sync_reset = "none";
defparam \data_bus[7]~I .output_sync_reset = "none";
defparam \data_bus[7]~I .oe_sync_reset = "none";
defparam \data_bus[7]~I .input_power_up = "low";
defparam \data_bus[7]~I .output_power_up = "low";
defparam \data_bus[7]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_M4
stratix_io \data_bus[6]~I (
	.datain(\uC_CTRL|data_out[6] ),
	.ddiodatain(),
	.oe(\uC_CTRL|i~3 ),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_bus[6]~1 ),
	.regout(),
	.ddioregout(),
	.padio(data_bus[6]));
// synopsys translate_off
defparam \data_bus[6]~I .operation_mode = "bidir";
defparam \data_bus[6]~I .ddio_mode = "none";
defparam \data_bus[6]~I .input_register_mode = "none";
defparam \data_bus[6]~I .output_register_mode = "none";
defparam \data_bus[6]~I .oe_register_mode = "none";
defparam \data_bus[6]~I .input_async_reset = "none";
defparam \data_bus[6]~I .output_async_reset = "none";
defparam \data_bus[6]~I .oe_async_reset = "none";
defparam \data_bus[6]~I .input_sync_reset = "none";
defparam \data_bus[6]~I .output_sync_reset = "none";
defparam \data_bus[6]~I .oe_sync_reset = "none";
defparam \data_bus[6]~I .input_power_up = "low";
defparam \data_bus[6]~I .output_power_up = "low";
defparam \data_bus[6]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_L3
stratix_io \data_bus[5]~I (
	.datain(\uC_CTRL|data_out[5] ),
	.ddiodatain(),
	.oe(\uC_CTRL|i~3 ),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_bus[5]~2 ),
	.regout(),
	.ddioregout(),
	.padio(data_bus[5]));
// synopsys translate_off
defparam \data_bus[5]~I .operation_mode = "bidir";
defparam \data_bus[5]~I .ddio_mode = "none";
defparam \data_bus[5]~I .input_register_mode = "none";
defparam \data_bus[5]~I .output_register_mode = "none";
defparam \data_bus[5]~I .oe_register_mode = "none";
defparam \data_bus[5]~I .input_async_reset = "none";
defparam \data_bus[5]~I .output_async_reset = "none";
defparam \data_bus[5]~I .oe_async_reset = "none";
defparam \data_bus[5]~I .input_sync_reset = "none";
defparam \data_bus[5]~I .output_sync_reset = "none";
defparam \data_bus[5]~I .oe_sync_reset = "none";
defparam \data_bus[5]~I .input_power_up = "low";
defparam \data_bus[5]~I .output_power_up = "low";
defparam \data_bus[5]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_P10
stratix_io \data_bus[4]~I (
	.datain(\uC_CTRL|data_out[4] ),
	.ddiodatain(),
	.oe(\uC_CTRL|i~3 ),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_bus[4]~3 ),
	.regout(),
	.ddioregout(),
	.padio(data_bus[4]));
// synopsys translate_off
defparam \data_bus[4]~I .operation_mode = "bidir";
defparam \data_bus[4]~I .ddio_mode = "none";
defparam \data_bus[4]~I .input_register_mode = "none";
defparam \data_bus[4]~I .output_register_mode = "none";
defparam \data_bus[4]~I .oe_register_mode = "none";
defparam \data_bus[4]~I .input_async_reset = "none";
defparam \data_bus[4]~I .output_async_reset = "none";
defparam \data_bus[4]~I .oe_async_reset = "none";
defparam \data_bus[4]~I .input_sync_reset = "none";
defparam \data_bus[4]~I .output_sync_reset = "none";
defparam \data_bus[4]~I .oe_sync_reset = "none";
defparam \data_bus[4]~I .input_power_up = "low";
defparam \data_bus[4]~I .output_power_up = "low";
defparam \data_bus[4]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_N6
stratix_io \data_bus[3]~I (
	.datain(\uC_CTRL|data_out[3] ),
	.ddiodatain(),
	.oe(\uC_CTRL|i~3 ),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_bus[3]~4 ),
	.regout(),
	.ddioregout(),
	.padio(data_bus[3]));
// synopsys translate_off
defparam \data_bus[3]~I .operation_mode = "bidir";
defparam \data_bus[3]~I .ddio_mode = "none";
defparam \data_bus[3]~I .input_register_mode = "none";
defparam \data_bus[3]~I .output_register_mode = "none";
defparam \data_bus[3]~I .oe_register_mode = "none";
defparam \data_bus[3]~I .input_async_reset = "none";
defparam \data_bus[3]~I .output_async_reset = "none";
defparam \data_bus[3]~I .oe_async_reset = "none";
defparam \data_bus[3]~I .input_sync_reset = "none";
defparam \data_bus[3]~I .output_sync_reset = "none";
defparam \data_bus[3]~I .oe_sync_reset = "none";
defparam \data_bus[3]~I .input_power_up = "low";
defparam \data_bus[3]~I .output_power_up = "low";
defparam \data_bus[3]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_N9
stratix_io \data_bus[2]~I (
	.datain(\uC_CTRL|data_out[2] ),
	.ddiodatain(),
	.oe(\uC_CTRL|i~3 ),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_bus[2]~5 ),
	.regout(),
	.ddioregout(),
	.padio(data_bus[2]));
// synopsys translate_off
defparam \data_bus[2]~I .operation_mode = "bidir";
defparam \data_bus[2]~I .ddio_mode = "none";
defparam \data_bus[2]~I .input_register_mode = "none";
defparam \data_bus[2]~I .output_register_mode = "none";
defparam \data_bus[2]~I .oe_register_mode = "none";
defparam \data_bus[2]~I .input_async_reset = "none";
defparam \data_bus[2]~I .output_async_reset = "none";
defparam \data_bus[2]~I .oe_async_reset = "none";
defparam \data_bus[2]~I .input_sync_reset = "none";
defparam \data_bus[2]~I .output_sync_reset = "none";
defparam \data_bus[2]~I .oe_sync_reset = "none";
defparam \data_bus[2]~I .input_power_up = "low";
defparam \data_bus[2]~I .output_power_up = "low";
defparam \data_bus[2]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_M5
stratix_io \data_bus[1]~I (
	.datain(\uC_CTRL|data_out[1] ),
	.ddiodatain(),
	.oe(\uC_CTRL|i~3 ),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_bus[1]~6 ),
	.regout(),
	.ddioregout(),
	.padio(data_bus[1]));
// synopsys translate_off
defparam \data_bus[1]~I .operation_mode = "bidir";
defparam \data_bus[1]~I .ddio_mode = "none";
defparam \data_bus[1]~I .input_register_mode = "none";
defparam \data_bus[1]~I .output_register_mode = "none";
defparam \data_bus[1]~I .oe_register_mode = "none";
defparam \data_bus[1]~I .input_async_reset = "none";
defparam \data_bus[1]~I .output_async_reset = "none";
defparam \data_bus[1]~I .oe_async_reset = "none";
defparam \data_bus[1]~I .input_sync_reset = "none";
defparam \data_bus[1]~I .output_sync_reset = "none";
defparam \data_bus[1]~I .oe_sync_reset = "none";
defparam \data_bus[1]~I .input_power_up = "low";
defparam \data_bus[1]~I .output_power_up = "low";
defparam \data_bus[1]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_N5
stratix_io \data_bus[0]~I (
	.datain(\uC_CTRL|data_out[0] ),
	.ddiodatain(),
	.oe(\uC_CTRL|i~3 ),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\data_bus[0]~7 ),
	.regout(),
	.ddioregout(),
	.padio(data_bus[0]));
// synopsys translate_off
defparam \data_bus[0]~I .operation_mode = "bidir";
defparam \data_bus[0]~I .ddio_mode = "none";
defparam \data_bus[0]~I .input_register_mode = "none";
defparam \data_bus[0]~I .output_register_mode = "none";
defparam \data_bus[0]~I .oe_register_mode = "none";
defparam \data_bus[0]~I .input_async_reset = "none";
defparam \data_bus[0]~I .output_async_reset = "none";
defparam \data_bus[0]~I .oe_async_reset = "none";
defparam \data_bus[0]~I .input_sync_reset = "none";
defparam \data_bus[0]~I .output_sync_reset = "none";
defparam \data_bus[0]~I .oe_sync_reset = "none";
defparam \data_bus[0]~I .input_power_up = "low";
defparam \data_bus[0]~I .output_power_up = "low";
defparam \data_bus[0]~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_T4
stratix_io \clk~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\clk~combout ),
	.regout(),
	.ddioregout(),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .operation_mode = "input";
defparam \clk~I .ddio_mode = "none";
defparam \clk~I .input_register_mode = "none";
defparam \clk~I .output_register_mode = "none";
defparam \clk~I .oe_register_mode = "none";
defparam \clk~I .input_async_reset = "none";
defparam \clk~I .output_async_reset = "none";
defparam \clk~I .oe_async_reset = "none";
defparam \clk~I .input_sync_reset = "none";
defparam \clk~I .output_sync_reset = "none";
defparam \clk~I .oe_sync_reset = "none";
defparam \clk~I .input_power_up = "low";
defparam \clk~I .output_power_up = "low";
defparam \clk~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_N10
stratix_io \r_w~I (
	.datain(),
	.ddiodatain(),
	.oe(gnd),
	.outclk(),
	.outclkena(vcc),
	.inclk(),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.delayctrlin(),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\r_w~combout ),
	.regout(),
	.ddioregout(),
	.padio(r_w));
// synopsys translate_off
defparam \r_w~I .operation_mode = "input";
defparam \r_w~I .ddio_mode = "none";
defparam \r_w~I .input_register_mode = "none";
defparam \r_w~I .output_register_mode = "none";
defparam \r_w~I .oe_register_mode = "none";
defparam \r_w~I .input_async_reset = "none";
defparam \r_w~I .output_async_reset = "none";
defparam \r_w~I .oe_async_reset = "none";
defparam \r_w~I .input_sync_reset = "none";
defparam \r_w~I .output_sync_reset = "none";
defparam \r_w~I .oe_sync_reset = "none";
defparam \r_w~I .input_power_up = "low";
defparam \r_w~I .output_power_up = "low";
defparam \r_w~I .oe_power_up = "low";
// synopsys translate_on

// atom is at Pin_U2
stratix_io \reset~I (