i2c.vo

IIc总线的源代码（vhdl语言）

// Copyright (C) 1991-2003 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 3.0 Build 199 06/26/2003 SJ Full Version"

// DATE "12/18/2003 15:31:40"

//
// Device: Altera EP1S40F1020C7 Package FBGA1020
// 

// 
// This Verilog file should be used for VCS only
// 

`timescale 1 ps/ 1 ps

module 	i2c (
	r_w,
	clk,
	reset,
	as,
	addr_bus,
	ds,
	sda,
	scl,
	data_bus,
	mcf,
	dtack,
	irq);
input 	r_w;
input 	clk;
input 	reset;
input 	as;
input 	[23:0] addr_bus;
input 	ds;
inout 	sda;
inout 	scl;
inout 	[7:0] data_bus;
inout 	mcf;
output 	dtack;
output 	irq;

supply0 gnd;
supply1 vcc;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("i2c_v.sdo");
// synopsys translate_on

wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|counter_cell[2]~COUT ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|counter_cell[1]~COUT ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|counter_cell[0]~COUT ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|counter_cell[2]~COUT ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|counter_cell[1]~COUT ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|counter_cell[0]~COUT ;
wire \I2C_CTRL|sda_out_reg_d1 ;
wire \I2C_CTRL|mbdr_i2c[7]~reg0 ;
wire \I2C_CTRL|mbdr_i2c[6]~reg0 ;
wire \I2C_CTRL|mbdr_i2c[5]~reg0 ;
wire \I2C_CTRL|mbdr_i2c[4]~reg0 ;
wire \I2C_CTRL|mbdr_i2c[3]~reg0 ;
wire \I2C_CTRL|mbdr_i2c[2]~reg0 ;
wire \I2C_CTRL|mbdr_i2c[1]~reg0 ;
wire \I2C_CTRL|mbdr_i2c[0]~reg0 ;
wire \I2C_CTRL|bus_busy_d1 ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[7] ;
wire \r_w~padio ;
wire \clk~padio ;
wire \reset~padio ;
wire \as~padio ;
wire \addr_bus[17]~padio ;
wire \addr_bus[9]~padio ;
wire \addr_bus[10]~padio ;
wire \addr_bus[18]~padio ;
wire \addr_bus[13]~padio ;
wire \addr_bus[14]~padio ;
wire \addr_bus[20]~padio ;
wire \addr_bus[23]~padio ;
wire \addr_bus[21]~padio ;
wire \addr_bus[8]~padio ;
wire \addr_bus[15]~padio ;
wire \addr_bus[16]~padio ;
wire \addr_bus[22]~padio ;
wire \addr_bus[11]~padio ;
wire \addr_bus[12]~padio ;
wire \addr_bus[19]~padio ;
wire \ds~padio ;
wire \addr_bus[1]~padio ;
wire \addr_bus[2]~padio ;
wire \addr_bus[7]~padio ;
wire \addr_bus[0]~padio ;
wire \addr_bus[5]~padio ;
wire \addr_bus[6]~padio ;
wire \addr_bus[4]~padio ;
wire \addr_bus[3]~padio ;
wire \sda~padio ;
wire \scl~padio ;
wire \data_bus[7]~padio ;
wire \data_bus[6]~padio ;
wire \data_bus[5]~padio ;
wire \data_bus[4]~padio ;
wire \data_bus[3]~padio ;
wire \data_bus[2]~padio ;
wire \data_bus[1]~padio ;
wire \data_bus[0]~padio ;
wire \dtack~padio ;
wire \irq~padio ;
wire \mcf~padio ;
wire \sda~0 ;
wire \scl~0 ;
wire \data_bus[7]~0 ;
wire \data_bus[6]~1 ;
wire \data_bus[5]~2 ;
wire \data_bus[4]~3 ;
wire \data_bus[3]~4 ;
wire \data_bus[2]~5 ;
wire \data_bus[1]~6 ;
wire \data_bus[0]~7 ;
wire \clk~combout ;
wire \r_w~combout ;
wire \reset~combout ;
wire \addr_bus[12]~combout ;
wire \addr_bus[15]~combout ;
wire \addr_bus[16]~combout ;
wire \addr_bus[21]~combout ;
wire \addr_bus[8]~combout ;
wire \uC_CTRL|i~3187 ;
wire \addr_bus[22]~combout ;
wire \addr_bus[11]~combout ;
wire \addr_bus[20]~combout ;
wire \addr_bus[23]~combout ;
wire \uC_CTRL|i~3218 ;
wire \uC_CTRL|i~3230 ;
wire \addr_bus[19]~combout ;
wire \as~combout ;
wire \addr_bus[18]~combout ;
wire \addr_bus[14]~combout ;
wire \addr_bus[13]~combout ;
wire \addr_bus[10]~combout ;
wire \uC_CTRL|i~3165 ;
wire \addr_bus[9]~combout ;
wire \addr_bus[17]~combout ;
wire \uC_CTRL|i~3212 ;
wire \ds~combout ;
wire \uC_CTRL|ds_int ;
wire \uC_CTRL|Select_71_rtl_1_rtl_21~1 ;
wire \uC_CTRL|prs_state~9 ;
wire \uC_CTRL|as_int ;
wire \uC_CTRL|Select_70_rtl_0~13 ;
wire \uC_CTRL|prs_state~11 ;
wire \uC_CTRL|Select_70_rtl_0~4 ;
wire \uC_CTRL|prs_state~8 ;
wire \uC_CTRL|as_int_d1 ;
wire \uC_CTRL|i~3229 ;
wire \uC_CTRL|address_match ;
wire \uC_CTRL|prs_state~10 ;
wire \addr_bus[4]~combout ;
wire \addr_bus[3]~combout ;
wire \uC_CTRL|i~3254 ;
wire \addr_bus[0]~combout ;
wire \addr_bus[6]~combout ;
wire \addr_bus[5]~combout ;
wire \addr_bus[7]~combout ;
wire \uC_CTRL|i~3241 ;
wire \addr_bus[2]~combout ;
wire \addr_bus[1]~combout ;
wire \uC_CTRL|i~3051 ;
wire \uC_CTRL|data_en ;
wire \uC_CTRL|i~252 ;
wire \uC_CTRL|data_in[5]~5 ;
wire \uC_CTRL|i~3248 ;
wire \uC_CTRL|i~3049 ;
wire \uC_CTRL|cntrl_en ;
wire \uC_CTRL|stat_en ;
wire \uC_CTRL|i~3052 ;
wire \uC_CTRL|data_in[7]~1 ;
wire \I2C_CTRL|mcf~reg0 ;
wire \uC_CTRL|data_in[4]~4 ;
wire \I2C_CTRL|sda_in ;
wire \I2C_CTRL|Select_396_rtl_11_rtl_30~10 ;
wire \I2C_CTRL|state~14 ;
wire \I2C_CTRL|Select_396_rtl_11_rtl_30~177 ;
wire \I2C_CTRL|Select_396_rtl_11_rtl_30~185 ;
wire \uC_CTRL|i~3273 ;
wire \uC_CTRL|addr_en ;
wire \uC_CTRL|data_in[6]~6 ;
wire \uC_CTRL|i~3050 ;
wire \uC_CTRL|i~211 ;
wire \uC_CTRL|i~1236 ;
wire \uC_CTRL|mbdr_micro[6]~reg0 ;
wire \uC_CTRL|mbdr_micro[5]~reg0 ;
wire \uC_CTRL|mbdr_micro[4]~reg0 ;
wire \I2C_CTRL|shift_reg_en ;
wire \uC_CTRL|i~202 ;
wire \uC_CTRL|data_in[3]~3 ;
wire \uC_CTRL|mbdr_micro[3]~reg0 ;
wire \uC_CTRL|mbdr_micro[0]~reg0 ;
wire \I2C_CTRL|I2CDATA_REG|i~166 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[0] ;
wire \I2C_CTRL|I2CDATA_REG|i~156 ;
wire \uC_CTRL|mbdr_micro[1]~reg0 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[1] ;
wire \I2C_CTRL|I2CDATA_REG|i~146 ;
wire \uC_CTRL|mbdr_micro[2]~reg0 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[2] ;
wire \I2C_CTRL|I2CDATA_REG|i~136 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[3] ;
wire \I2C_CTRL|I2CDATA_REG|i~126 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[4] ;
wire \I2C_CTRL|I2CDATA_REG|i~116 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[5] ;
wire \I2C_CTRL|I2CDATA_REG|i~106 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[6] ;
wire \uC_CTRL|mbcr_wr~reg0 ;
wire \I2C_CTRL|maas~reg0 ;
wire \I2C_CTRL|i~1122 ;
wire \uC_CTRL|i~3105 ;
wire \uC_CTRL|i~1239 ;
wire \uC_CTRL|data_out[6] ;
wire \uC_CTRL|madr[6]~reg0 ;
wire \uC_CTRL|i~1408 ;
wire \uC_CTRL|mif_bit_reset~1 ;
wire \uC_CTRL|mal_bit_reset~reg0 ;
wire \I2C_CTRL|gen_start ;
wire \I2C_CTRL|i~1253 ;
wire \I2C_CTRL|i~1121 ;
wire \I2C_CTRL|Select_408~33 ;
wire \I2C_CTRL|bit_cnt_ld~1 ;
wire \I2C_CTRL|sm_stop ;
wire \I2C_CTRL|i~66 ;
wire \I2C_CTRL|i~1242 ;
wire \I2C_CTRL|scl_in ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[0]~COUT0 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[0]~COUT1 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[1] ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[1]~COUT0 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[1]~COUT1 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[2] ;
wire \I2C_CTRL|reduce_nor_91~6 ;
wire \I2C_CTRL|scl_state~10 ;
wire \I2C_CTRL|scl_state~11 ;
wire \I2C_CTRL|Select_150_rtl_8_rtl_27~73 ;
wire \I2C_CTRL|scl_state~12 ;
wire \I2C_CTRL|bit_cnt_ld~0 ;
wire \I2C_CTRL|Select_140_rtl_19~4 ;
wire \I2C_CTRL|i~1126 ;
wire \I2C_CTRL|Select_140_rtl_19~1 ;
wire \I2C_CTRL|stop_scl_reg ;
wire \I2C_CTRL|Select_152_rtl_9_rtl_28~55 ;
wire \I2C_CTRL|Select_152_rtl_9_rtl_28~64 ;
wire \I2C_CTRL|scl_state~13 ;
wire \I2C_CTRL|Select_160_rtl_18~54 ;
wire \I2C_CTRL|Select_160_rtl_18~10 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[0] ;
wire \I2C_CTRL|reduce_nor_71~7 ;
wire \I2C_CTRL|Select_144_rtl_5~4 ;
wire \I2C_CTRL|Select_144_rtl_5~62 ;
wire \I2C_CTRL|scl_state~9 ;
wire \uC_CTRL|data_in[2]~0 ;
wire \uC_CTRL|rsta~reg0 ;
wire \I2C_CTRL|i~1258 ;
wire \I2C_CTRL|mal~reg0 ;
wire \uC_CTRL|i~3119 ;
wire \uC_CTRL|i~1411 ;
wire \uC_CTRL|data_out[4] ;
wire \uC_CTRL|madr[4]~reg0 ;
wire \uC_CTRL|i~1322 ;
wire \uC_CTRL|i~3112 ;
wire \uC_CTRL|i~1325 ;
wire \uC_CTRL|data_out[5] ;
wire \uC_CTRL|madr[5]~reg0 ;
wire \uC_CTRL|i~1463 ;
wire \uC_CTRL|txak~reg0 ;
wire \uC_CTRL|i~3044 ;
wire \uC_CTRL|i~1469 ;
wire \uC_CTRL|data_out[3] ;
wire \uC_CTRL|madr[3]~reg0 ;
wire \I2C_CTRL|i2c_header_en ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[3] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[4] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[5] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[6] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[0] ;
wire \uC_CTRL|data_in[1]~2 ;
wire \uC_CTRL|mif_bit_reset~reg0 ;
wire \I2C_CTRL|i~1178 ;
wire \I2C_CTRL|mif~reg0 ;
wire \uC_CTRL|i~1604 ;
wire \uC_CTRL|i~1598 ;
wire \uC_CTRL|data_out[1] ;
wire \uC_CTRL|madr[1]~reg0 ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[1] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[2] ;
wire \I2C_CTRL|i~107 ;
wire \I2C_CTRL|reduce_nor_297~14 ;
wire \uC_CTRL|i~1150 ;
wire \uC_CTRL|i~1153 ;
wire \uC_CTRL|data_out[7] ;
wire \uC_CTRL|madr[7]~reg0 ;
wire \uC_CTRL|i~1551 ;
wire \I2C_CTRL|srw~reg0 ;
wire \uC_CTRL|i~3126 ;
wire \uC_CTRL|i~1554 ;
wire \uC_CTRL|data_out[2] ;
wire \uC_CTRL|madr[2]~reg0 ;
wire \I2C_CTRL|reduce_nor_297~19 ;
wire \I2C_CTRL|reduce_nor_297~11 ;
wire \I2C_CTRL|reduce_nor_297~31 ;
wire \I2C_CTRL|state~8 ;
wire \I2C_CTRL|i~572 ;
wire \I2C_CTRL|i~1320 ;
wire \I2C_CTRL|shift_reg_ld ;
wire \uC_CTRL|mbdr_micro[7]~reg0 ;
wire \I2C_CTRL|I2CDATA_REG|i~96 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[7] ;
wire \uC_CTRL|i~3098 ;
wire \uC_CTRL|men~reg0 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[2]~COUT0 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[2]~COUT1 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_36|wysi_counter|safe_q[3] ;
wire \I2C_CTRL|reduce_nor_71~0 ;
wire \I2C_CTRL|Select_144_rtl_5~51 ;
wire \I2C_CTRL|i~1194 ;
wire \I2C_CTRL|Select_154_rtl_10_rtl_29~15 ;
wire \I2C_CTRL|scl_state~14 ;
wire \I2C_CTRL|i~1190 ;
wire \I2C_CTRL|Select_142_rtl_4_rtl_24~50 ;
wire \I2C_CTRL|Select_142_rtl_4_rtl_24~16 ;
wire \I2C_CTRL|Select_142_rtl_4_rtl_24~75 ;
wire \I2C_CTRL|scl_state~8 ;
wire \I2C_CTRL|i~1306 ;
wire \I2C_CTRL|i~1217 ;
wire \I2C_CTRL|i~1226 ;
wire \I2C_CTRL|msta_rst~reg0 ;
wire \uC_CTRL|msta~reg0 ;
wire \I2C_CTRL|msta_d1 ;
wire \I2C_CTRL|i~239 ;
wire \I2C_CTRL|gen_stop ;
wire \I2C_CTRL|detect_stop ;
wire \I2C_CTRL|i~112 ;
wire \I2C_CTRL|state~12 ;
wire \I2C_CTRL|Select_401_rtl_14_rtl_32~100 ;
wire \I2C_CTRL|Select_404_rtl_16_rtl_34~51 ;
wire \I2C_CTRL|Select_401_rtl_14_rtl_32~111 ;
wire \I2C_CTRL|Select_401_rtl_14_rtl_32~15 ;
wire \I2C_CTRL|state~11 ;
wire \I2C_CTRL|bit_cnt_en~0 ;
wire \I2C_CTRL|bit_cnt_ld ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[0] ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[0]~COUT0 ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[0]~COUT1 ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[1] ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[1]~COUT0 ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[1]~COUT1 ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[2] ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[2]~COUT0 ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[2]~COUT1 ;
wire \I2C_CTRL|BITCNT|q_int_rtl_37|wysi_counter|safe_q[3] ;
wire \I2C_CTRL|reduce_nor_221~19 ;
wire \I2C_CTRL|Select_398_rtl_12~5 ;
wire \I2C_CTRL|state~9 ;
wire \I2C_CTRL|state~10 ;
wire \uC_CTRL|mtx~reg0 ;
wire \I2C_CTRL|Select_404_rtl_16_rtl_34~10 ;
wire \I2C_CTRL|Select_404_rtl_16_rtl_34~65 ;
wire \I2C_CTRL|Select_404_rtl_16_rtl_34~5 ;
wire \I2C_CTRL|i~65 ;
wire \I2C_CTRL|Select_404_rtl_16_rtl_34~74 ;
wire \I2C_CTRL|state~13 ;
wire \I2C_CTRL|detect_start ;
wire \I2C_CTRL|bus_busy ;
wire \I2C_CTRL|master_slave ;
wire \I2C_CTRL|i~510 ;
wire \I2C_CTRL|Select_138_rtl_20~181 ;
wire \I2C_CTRL|Select_138_rtl_20~198 ;
wire \I2C_CTRL|Select_138_rtl_20~209 ;
wire \I2C_CTRL|Select_138_rtl_20~212 ;
wire \I2C_CTRL|i~1119 ;
wire \I2C_CTRL|master_sda ;
wire \I2C_CTRL|i~1123 ;
wire \I2C_CTRL|i~1203 ;
wire \I2C_CTRL|sda_out_reg ;
wire \I2C_CTRL|i~1219 ;
wire \I2C_CTRL|i~449 ;
wire \I2C_CTRL|arb_lost ;
wire \I2C_CTRL|i~3 ;
wire \I2C_CTRL|i~160 ;
wire \I2C_CTRL|slave_sda ;
wire \I2C_CTRL|sda_oe ;
wire \I2C_CTRL|scl_out_reg ;
wire \uC_CTRL|i~3 ;
wire \uC_CTRL|i~2312 ;
wire \I2C_CTRL|rxak~reg0 ;
wire \uC_CTRL|i~2315 ;
wire \uC_CTRL|data_out[0] ;
wire \uC_CTRL|dtack_int ;
wire \uC_CTRL|i~30 ;
wire \uC_CTRL|mien~reg0 ;
wire \uC_CTRL|i~0 ;


// atom is at Pin_K2
stratix_io \sda~I (
	.datain(\I2C_CTRL|sda_oe ),
	.ddiodatain(),
	.oe(vcc),
	.outclk(),