i2c.vo

IIc总线的源代码（vhdl语言）

// Copyright (C) 1991-2004 Altera Corporation
// Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
// support information,  device programming or simulation file,  and any other
// associated  documentation or information  provided by  Altera  or a partner
// under  Altera's   Megafunction   Partnership   Program  may  be  used  only
// to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
// other  use  of such  megafunction  design,  netlist,  support  information,
// device programming or simulation file,  or any other  related documentation
// or information  is prohibited  for  any  other purpose,  including, but not
// limited to  modification,  reverse engineering,  de-compiling, or use  with
// any other  silicon devices,  unless such use is  explicitly  licensed under
// a separate agreement with  Altera  or a megafunction partner.  Title to the
// intellectual property,  including patents,  copyrights,  trademarks,  trade
// secrets,  or maskworks,  embodied in any such megafunction design, netlist,
// support  information,  device programming or simulation file,  or any other
// related documentation or information provided by  Altera  or a megafunction
// partner, remains with Altera, the megafunction partner, or their respective
// licensors. No other licenses, including any licenses needed under any third
// party's intellectual property, are provided herein.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 4.2 Build 157 12/07/2004 SJ Full Version"

// DATE "12/23/2004 10:46:04"

// 
// Device: Altera EP20K60EFC144-1X Package FBGA144
// 

// 
// This Verilog file should be used for ModelSim-Altera (Verilog) only
// 

`timescale 1 ps/ 1 ps

module 	i2c (
	clk,
	reset,
	as,
	r_w,
	addr_bus,
	ds,
	sda,
	scl,
	data_bus,
	mcf,
	dtack,
	irq);
input 	clk;
input 	reset;
input 	as;
input 	r_w;
input 	[23:0] addr_bus;
input 	ds;
inout 	sda;
inout 	scl;
inout 	[7:0] data_bus;
inout 	mcf;
output 	dtack;
output 	irq;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("i2c_v.sdo");
// synopsys translate_on

wire \uC_CTRL|mif_bit_reset ;
wire \uC_CTRL|mal_bit_reset ;
wire \uC_CTRL|mif_bit_reset~3 ;
wire \uC_CTRL|data_out~2485 ;
wire \uC_CTRL|data_out~2508 ;
wire \I2C_CTRL|mbdr_i2c[1]~reg0 ;
wire \I2C_CTRL|rxak ;
wire \I2C_CTRL|gen_stop~4 ;
wire \I2C_CTRL|reduce_nor~149 ;
wire \I2C_CTRL|next_scl_state.scl_idle~83 ;
wire \uC_CTRL|data_en~58 ;
wire \uC_CTRL|SYNCH_INPUTS~161 ;
wire \uC_CTRL|SYNCH_INPUTS~163 ;
wire \I2C_CTRL|reduce_nor~150 ;
wire \I2C_CTRL|i2cdata_reg_ctrl~90 ;
wire \I2C_CTRL|master_sda ;
wire \I2C_CTRL|sda_out~358 ;
wire \I2C_CTRL|arb_lost~188 ;
wire \I2C_CTRL|arb_lost~191 ;
wire \I2C_CTRL|master_sda~90 ;
wire \addr_bus[12]~combout ;
wire \addr_bus[7]~combout ;
wire \addr_bus[1]~combout ;
wire \addr_bus[17]~combout ;
wire \addr_bus[13]~combout ;
wire \addr_bus[20]~combout ;
wire \addr_bus[21]~combout ;
wire \sda~0 ;
wire \scl~0 ;
wire \data_bus[7]~0 ;
wire \data_bus[6]~1 ;
wire \data_bus[5]~2 ;
wire \data_bus[4]~3 ;
wire \data_bus[3]~4 ;
wire \data_bus[2]~5 ;
wire \data_bus[1]~6 ;
wire \data_bus[0]~7 ;
wire \as~combout ;
wire \clk~combout ;
wire \reset~combout ;
wire \uC_CTRL|as_int ;
wire \uC_CTRL|as_int_d1 ;
wire \ds~combout ;
wire \uC_CTRL|ds_int ;
wire \uC_CTRL|prs_state.assert_dtack ;
wire \uC_CTRL|dtack_int ;
wire \addr_bus[19]~combout ;
wire \addr_bus[15]~combout ;
wire \addr_bus[8]~combout ;
wire \addr_bus[16]~combout ;
wire \addr_bus[23]~combout ;
wire \addr_bus[22]~combout ;
wire \addr_bus[11]~combout ;
wire \uC_CTRL|SYNCH_INPUTS~163_cascout ;
wire \uC_CTRL|SYNCH_INPUTS~166 ;
wire \addr_bus[18]~combout ;
wire \addr_bus[14]~combout ;
wire \addr_bus[10]~combout ;
wire \addr_bus[9]~combout ;
wire \uC_CTRL|SYNCH_INPUTS~161_cascout ;
wire \uC_CTRL|SYNCH_INPUTS~165 ;
wire \uC_CTRL|address_match ;
wire \uC_CTRL|next_state.idle~86 ;
wire \uC_CTRL|next_state.idle~85 ;
wire \uC_CTRL|prs_state.idle ;
wire \uC_CTRL|next_state.addr~13 ;
wire \uC_CTRL|prs_state.addr ;
wire \uC_CTRL|dtack_oe~0 ;
wire \uC_CTRL|prs_state.data_trs ;
wire \r_w~combout ;
wire \addr_bus[3]~combout ;
wire \addr_bus[4]~combout ;
wire \uC_CTRL|data_en~57 ;
wire \addr_bus[2]~combout ;
wire \addr_bus[0]~combout ;
wire \addr_bus[5]~combout ;
wire \addr_bus[6]~combout ;
wire \uC_CTRL|data_en~55 ;
wire \uC_CTRL|data_en~56 ;
wire \uC_CTRL|cntrl_en ;
wire \uC_CTRL|men~48 ;
wire \uC_CTRL|mien~reg0 ;
wire \uC_CTRL|men~reg0 ;
wire \I2C_CTRL|sda_in ;
wire \I2C_CTRL|stop_det~0 ;
wire \I2C_CTRL|detect_stop ;
wire \I2C_CTRL|state_machine~0 ;
wire \I2C_CTRL|state.wait_ack ;
wire \I2C_CTRL|state.ack_data ;
wire \I2C_CTRL|scl_generator_comb~49 ;
wire \I2C_CTRL|sda_oe~27 ;
wire \I2C_CTRL|Select~719 ;
wire \I2C_CTRL|sm_stop ;
wire \I2C_CTRL|msta_d1 ;
wire \I2C_CTRL|gen_stop ;
wire \I2C_CTRL|mal~141 ;
wire \I2C_CTRL|next_scl_state.scl_idle~84 ;
wire \I2C_CTRL|scl_in ;
wire \I2C_CTRL|scl_state.scl_high_edge ;
wire \I2C_CTRL|stop_scl~12 ;
wire \I2C_CTRL|scl_state.scl_low ;
wire \I2C_CTRL|stop_scl~77 ;
wire \I2C_CTRL|stop_scl_reg ;
wire \I2C_CTRL|next_scl_state.scl_high~96 ;
wire \I2C_CTRL|clk_cnt_rst~62 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_1|wysi_counter|counter_cell[0]~COUT ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_1|wysi_counter|sload_path[1] ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_1|wysi_counter|sload_path[0] ;
wire \I2C_CTRL|reduce_nor~147 ;
wire \I2C_CTRL|next_scl_state.scl_high~12 ;
wire \I2C_CTRL|next_scl_state.scl_high~97 ;
wire \I2C_CTRL|scl_state.scl_high ;
wire \I2C_CTRL|scl_state.scl_low_edge ;
wire \I2C_CTRL|reduce_or~21 ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_1|wysi_counter|counter_cell[1]~COUT ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_1|wysi_counter|sload_path[2] ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_1|wysi_counter|counter_cell[2]~COUT ;
wire \I2C_CTRL|CLKCNT|q_int_rtl_1|wysi_counter|sload_path[3] ;
wire \I2C_CTRL|reduce_nor~148 ;
wire \I2C_CTRL|gen_start ;
wire \I2C_CTRL|next_scl_state.start~78 ;
wire \I2C_CTRL|next_scl_state.start~79 ;
wire \I2C_CTRL|scl_state.start ;
wire \uC_CTRL|mbcr_wr~36 ;
wire \uC_CTRL|rsta~reg0 ;
wire \I2C_CTRL|sda_out~357 ;
wire \I2C_CTRL|sda_out~358_cascout ;
wire \I2C_CTRL|sda_out~360 ;
wire \I2C_CTRL|next_scl_state.scl_idle~85 ;
wire \I2C_CTRL|next_scl_state.stop_wait~12 ;
wire \I2C_CTRL|scl_state.stop_wait ;
wire \I2C_CTRL|sda_out~351 ;
wire \I2C_CTRL|sda_out~352 ;
wire \I2C_CTRL|sda_out_reg ;
wire \I2C_CTRL|sda_out_reg_d1 ;
wire \I2C_CTRL|Select~715 ;
wire \I2C_CTRL|Select~714 ;
wire \I2C_CTRL|Select~716 ;
wire \I2C_CTRL|i2c_header_en ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[0] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[1] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[2] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[3] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[4] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[5] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[6] ;
wire \I2C_CTRL|I2CHEADER_REG|data_int[7] ;
wire \uC_CTRL|addr_en~31 ;
wire \uC_CTRL|addr_en ;
wire \uC_CTRL|madr[1]~68 ;
wire \uC_CTRL|madr[2]~reg0 ;
wire \I2C_CTRL|reduce_nor~142 ;
wire \uC_CTRL|madr[1]~reg0 ;
wire \uC_CTRL|madr[5]~reg0 ;
wire \I2C_CTRL|reduce_nor~150_cascout ;
wire \I2C_CTRL|reduce_nor~154 ;
wire \I2C_CTRL|reduce_nor~143 ;
wire \I2C_CTRL|state.idle ;
wire \I2C_CTRL|arb_lost~188_cascout ;
wire \I2C_CTRL|arb_lost~191_cascout ;
wire \I2C_CTRL|arb_lost~190 ;
wire \I2C_CTRL|arb_lost ;
wire \I2C_CTRL|next_scl_state.start~77 ;
wire \I2C_CTRL|next_scl_state.scl_idle~86 ;
wire \I2C_CTRL|scl_state.scl_idle ;
wire \I2C_CTRL|msta_rst ;
wire \uC_CTRL|msta~reg0 ;
wire \I2C_CTRL|master_slave ;
wire \uC_CTRL|mtx~reg0 ;
wire \I2C_CTRL|Select~704 ;
wire \I2C_CTRL|Select~707 ;
wire \I2C_CTRL|Select~706 ;
wire \uC_CTRL|madr[3]~reg0 ;
wire \I2C_CTRL|addr_match~2 ;
wire \I2C_CTRL|state~229 ;
wire \I2C_CTRL|state.rcv_data ;
wire \I2C_CTRL|bit_cnt_en~1 ;
wire \I2C_CTRL|bit_cnt_ld~3 ;
wire \I2C_CTRL|BITCNT|q_int_rtl_0|wysi_counter|counter_cell[0]~COUT ;
wire \I2C_CTRL|BITCNT|q_int_rtl_0|wysi_counter|counter_cell[1]~COUT ;
wire \I2C_CTRL|BITCNT|q_int_rtl_0|wysi_counter|counter_cell[2]~COUT ;
wire \I2C_CTRL|BITCNT|q_int_rtl_0|wysi_counter|sload_path[3] ;
wire \I2C_CTRL|BITCNT|q_int_rtl_0|wysi_counter|sload_path[2] ;
wire \I2C_CTRL|BITCNT|q_int_rtl_0|wysi_counter|sload_path[0] ;
wire \I2C_CTRL|reduce_nor~141 ;
wire \I2C_CTRL|state.ack_header ;
wire \I2C_CTRL|Select~703 ;
wire \I2C_CTRL|Select~701 ;
wire \I2C_CTRL|Select~702 ;
wire \I2C_CTRL|reduce_nor~156 ;
wire \I2C_CTRL|Select~720 ;
wire \I2C_CTRL|state.xmit_data ;
wire \I2C_CTRL|Select~709 ;
wire \I2C_CTRL|state.header ;
wire \I2C_CTRL|start_det~0 ;
wire \I2C_CTRL|detect_start ;
wire \I2C_CTRL|mbb ;
wire \I2C_CTRL|bus_busy_d1 ;
wire \I2C_CTRL|mal~138 ;
wire \I2C_CTRL|mal~137 ;
wire \I2C_CTRL|mal~139 ;
wire \I2C_CTRL|mal~reg0 ;
wire \I2C_CTRL|BITCNT|q_int_rtl_0|wysi_counter|sload_path[1] ;
wire \I2C_CTRL|mcf~reg0 ;
wire \uC_CTRL|mbcr_wr ;
wire \I2C_CTRL|maas~reg0 ;
wire \I2C_CTRL|mif~60 ;
wire \I2C_CTRL|mif ;
wire \uC_CTRL|irq~0 ;
wire \I2C_CTRL|sda_oe~25 ;
wire \uC_CTRL|data_en ;
wire \uC_CTRL|mbdr_micro[7]~50 ;
wire \uC_CTRL|mbdr_micro[7]~reg0 ;
wire \I2C_CTRL|i2cdata_reg_ctrl~91 ;
wire \I2C_CTRL|shift_reg_ld ;
wire \I2C_CTRL|shift_reg_en ;
wire \uC_CTRL|mbdr_micro[6]~reg0 ;
wire \I2C_CTRL|I2CDATA_REG|data_int~983 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[6] ;
wire \I2C_CTRL|I2CDATA_REG|data_int~981 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[7] ;
wire \I2C_CTRL|slv_mas_sda~1 ;
wire \I2C_CTRL|slave_sda ;
wire \I2C_CTRL|slave_sda~168 ;
wire \I2C_CTRL|sda_oe~4 ;
wire \I2C_CTRL|scl_out_reg ;
wire \uC_CTRL|stat_en ;
wire \uC_CTRL|data_out~2489 ;
wire \uC_CTRL|madr[7]~reg0 ;
wire \uC_CTRL|data_out~2486 ;
wire \I2C_CTRL|mbdr_i2c_proc~2 ;
wire \I2C_CTRL|mbdr_i2c[7]~reg0 ;
wire \uC_CTRL|data_out~2484 ;
wire \uC_CTRL|data_out~2487 ;
wire \uC_CTRL|data_out~2488 ;
wire \uC_CTRL|data_out[7] ;
wire \uC_CTRL|data_bus~8 ;
wire \I2C_CTRL|mbdr_i2c[6]~reg0 ;
wire \uC_CTRL|data_out~2491 ;
wire \uC_CTRL|madr[6]~reg0 ;
wire \uC_CTRL|data_out~2492 ;
wire \uC_CTRL|data_out~2493 ;
wire \uC_CTRL|data_out~2494 ;
wire \uC_CTRL|data_out[6] ;
wire \uC_CTRL|data_out~2497 ;
wire \uC_CTRL|mbdr_micro[5]~reg0 ;
wire \uC_CTRL|mbdr_micro[4]~reg0 ;
wire \uC_CTRL|mbdr_micro[1]~reg0 ;
wire \uC_CTRL|mbdr_micro[0]~reg0 ;
wire \I2C_CTRL|I2CDATA_REG|data_int~995 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[0] ;
wire \I2C_CTRL|I2CDATA_REG|data_int~993 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[1] ;
wire \I2C_CTRL|I2CDATA_REG|data_int~991 ;
wire \uC_CTRL|mbdr_micro[2]~reg0 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[2] ;
wire \I2C_CTRL|I2CDATA_REG|data_int~989 ;
wire \uC_CTRL|mbdr_micro[3]~reg0 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[3] ;
wire \I2C_CTRL|I2CDATA_REG|data_int~987 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[4] ;
wire \I2C_CTRL|I2CDATA_REG|data_int~985 ;
wire \I2C_CTRL|I2CDATA_REG|data_int[5] ;
wire \I2C_CTRL|mbdr_i2c[5]~reg0 ;
wire \uC_CTRL|data_out~2496 ;
wire \uC_CTRL|data_out~2498 ;
wire \uC_CTRL|data_out~2499 ;
wire \uC_CTRL|data_out[5] ;
wire \uC_CTRL|madr[4]~reg0 ;
wire \uC_CTRL|data_out~2502 ;
wire \I2C_CTRL|mbdr_i2c[4]~reg0 ;
wire \uC_CTRL|data_out~2501 ;
wire \uC_CTRL|data_out~2503 ;
wire \uC_CTRL|data_out~2504 ;
wire \uC_CTRL|data_out[4] ;
wire \I2C_CTRL|mbdr_i2c[3]~reg0 ;
wire \uC_CTRL|data_out~2511 ;
wire \uC_CTRL|data_out~2506 ;
wire \uC_CTRL|data_out~2507 ;
wire \uC_CTRL|txak~reg0 ;
wire \uC_CTRL|data_out~2509 ;
wire \uC_CTRL|data_out~2510 ;
wire \uC_CTRL|data_out[3] ;
wire \I2C_CTRL|mbdr_i2c[2]~reg0 ;
wire \uC_CTRL|data_out~2513 ;
wire \uC_CTRL|data_out~2514 ;
wire \I2C_CTRL|srw~reg0 ;
wire \uC_CTRL|data_out~2515 ;
wire \uC_CTRL|data_out~2516 ;
wire \uC_CTRL|data_out[2] ;
wire \uC_CTRL|data_out~2518 ;
wire \uC_CTRL|data_out~2529 ;
wire \uC_CTRL|data_out~2528 ;
wire \uC_CTRL|data_out~2519 ;
wire \uC_CTRL|data_out[1] ;
wire \I2C_CTRL|mbdr_i2c[0]~reg0 ;
wire \uC_CTRL|data_out~2521 ;
wire \uC_CTRL|data_out~2522 ;
wire \uC_CTRL|data_out[0]~1093 ;
wire \uC_CTRL|data_out[0] ;


// atom is at LC9_1_E2
apex20ke_lcell \uC_CTRL|mif_bit_reset~I (
// Equation(s):
// \uC_CTRL|mif_bit_reset  = DFFE(!\r_w~combout  & \uC_CTRL|mif_bit_reset  # !\data_bus[2]~5 , GLOBAL(\clk~combout ), GLOBAL(\reset~combout ), , \uC_CTRL|mif_bit_reset~3 )

	.dataa(\r_w~combout ),
	.datab(\uC_CTRL|mif_bit_reset ),
	.datac(vcc),
	.datad(\data_bus[2]~5 ),
	.cin(gnd),
	.cascin(vcc),
	.clk(\clk~combout ),
	.aclr(!\reset~combout ),
	.ena(\uC_CTRL|mif_bit_reset~3 ),
	.sclr(gnd),
	.sload(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\uC_CTRL|mif_bit_reset ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \uC_CTRL|mif_bit_reset~I .operation_mode = "normal";
defparam \uC_CTRL|mif_bit_reset~I .packed_mode = "false";
defparam \uC_CTRL|mif_bit_reset~I .lut_mask = "4455";
defparam \uC_CTRL|mif_bit_reset~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at PIN_C11
apex20ke_io \addr_bus[12]~I (
	.datain(gnd),
	.clk(gnd),
	.aclr(gnd),
	.ena(vcc),
	.oe(gnd),
	.preset(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.devoe(devoe),
	.combout(\addr_bus[12]~combout ),
	.regout(),
	.padio(addr_bus[12]));
// synopsys translate_off
defparam \addr_bus[12]~I .operation_mode = "input";
defparam \addr_bus[12]~I .reg_source_mode = "none";
defparam \addr_bus[12]~I .feedback_mode = "from_pin";
defparam \addr_bus[12]~I .power_up = "low";
// synopsys translate_on

// atom is at LC5_1_E2
apex20ke_lcell \uC_CTRL|mal_bit_reset~I (
// Equation(s):
// \uC_CTRL|mal_bit_reset  = DFFE(!\r_w~combout  & \uC_CTRL|mal_bit_reset  # !\data_bus[4]~3 , GLOBAL(\clk~combout ), GLOBAL(\reset~combout ), , \uC_CTRL|mif_bit_reset~3 )

	.dataa(vcc),
	.datab(\data_bus[4]~3 ),
	.datac(\r_w~combout ),
	.datad(\uC_CTRL|mal_bit_reset ),
	.cin(gnd),
	.cascin(vcc),
	.clk(\clk~combout ),
	.aclr(!\reset~combout ),
	.ena(\uC_CTRL|mif_bit_reset~3 ),
	.sclr(gnd),
	.sload(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\uC_CTRL|mal_bit_reset ),
	.cout(),
	.cascout());
// synopsys translate_off
defparam \uC_CTRL|mal_bit_reset~I .operation_mode = "normal";
defparam \uC_CTRL|mal_bit_reset~I .packed_mode = "false";
defparam \uC_CTRL|mal_bit_reset~I .lut_mask = "0F03";
defparam \uC_CTRL|mal_bit_reset~I .output_mode = "reg_only";
// synopsys translate_on

// atom is at LC5_3_H2
apex20ke_lcell \uC_CTRL|mif_bit_reset~3_I (
// Equation(s):
// \uC_CTRL|mif_bit_reset~3  = \uC_CTRL|stat_en  & \uC_CTRL|prs_state.data_trs 

	.dataa(vcc),
	.datab(vcc),
	.datac(\uC_CTRL|stat_en ),
	.datad(\uC_CTRL|prs_state.data_trs ),