a8255.map.rpt

8255的vhdl代码

+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 122   ;
;                                             ;       ;
; Total combinational functions               ; 122   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 78    ;
;     -- 3 input functions                    ; 27    ;
;     -- <=2 input functions                  ; 17    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 122   ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 54    ;
;     -- Dedicated logic registers            ; 54    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 81    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 54    ;
; Total fan-out                               ; 670   ;
; Average fan-out                             ; 2.61  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name        ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------+--------------+
; |a8255                     ; 122 (0)           ; 54 (0)       ; 0           ; 0            ; 0       ; 0         ; 81   ; 0            ; |a8255                     ; work         ;
;    |cntl_log:I_cntl_log|   ; 36 (36)           ; 7 (7)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |a8255|cntl_log:I_cntl_log ; work         ;
;    |dout_mux:I_dout_mux|   ; 33 (33)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |a8255|dout_mux:I_dout_mux ; work         ;
;    |portain:I_portain|     ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |a8255|portain:I_portain   ; work         ;
;    |portaout:I_portaout|   ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |a8255|portaout:I_portaout ; work         ;
;    |portbin:I_portbin|     ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |a8255|portbin:I_portbin   ; work         ;
;    |portbout:I_portbout|   ; 0 (0)             ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |a8255|portbout:I_portbout ; work         ;
;    |portcout:I_portcout|   ; 53 (53)           ; 15 (15)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |a8255|portcout:I_portcout ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+----------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 54    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 3     ;
; Number of registers using Asynchronous Clear ; 54    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 39    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; cntl_log:I_cntl_log|ControlRegQ[0]     ; 4       ;
; cntl_log:I_cntl_log|ControlRegQ[1]     ; 5       ;
; cntl_log:I_cntl_log|ControlRegQ[3]     ; 5       ;
; cntl_log:I_cntl_log|ControlRegQ[4]     ; 14      ;
; Total number of inverted registers = 4 ;         ;
+----------------------------------------+---------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output               ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+
; 3:1                ; 8 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |a8255|cntl_log:I_cntl_log|PortCOutLd[3] ;
; 8:1                ; 4 bits    ; 20 LEs        ; 16 LEs               ; 4 LEs                  ; No         ; |a8255|dout_mux:I_dout_mux|Mux6          ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |a8255|cntl_log:I_cntl_log|PCEN[5]       ;
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |a8255|cntl_log:I_cntl_log|PCEN[7]       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Thu Jun 12 18:18:33 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255
Info: Found 2 design units, including 1 entities, in source file CNTL_LOG.VHD
    Info: Found design unit 1: cntl_log-rtl
    Info: Found entity 1: cntl_log
Info: Found 2 design units, including 1 entities, in source file DOUT_MUX.VHD
    Info: Found design unit 1: dout_mux-rtl
    Info: Found entity 1: dout_mux
Info: Found 2 design units, including 1 entities, in source file PORTAIN.VHD
    Info: Found design unit 1: portain-rtl
    Info: Found entity 1: portain
Info: Found 2 design units, including 1 entities, in source file PORTAOUT.VHD
    Info: Found design unit 1: portaout-rtl
    Info: Found entity 1: portaout
Info: Found 2 design units, including 1 entities, in source file PORTBIN.VHD
    Info: Found design unit 1: portbin-rtl
    Info: Found entity 1: portbin
Info: Found 2 design units, including 1 entities, in source file PORTBOUT.VHD
    Info: Found design unit 1: portbout-rtl
    Info: Found entity 1: portbout
Info: Found 2 design units, including 1 entities, in source file PORTCOUT.VHD
    Info: Found design unit 1: portcout-rtl
    Info: Found entity 1: portcout
Info: Found 2 design units, including 1 entities, in source file A8255.vhd
    Info: Found design unit 1: a8255-structure
    Info: Found entity 1: a8255
Info: Elaborating entity "A8255" for the top level hierarchy
Info: Elaborating entity "dout_mux" for hierarchy "dout_mux:I_dout_mux"
Warning (10812): VHDL warning at DOUT_MUX.VHD(22): sensitivity list already contains DOUTSelect
Info: Elaborating entity "cntl_log" for hierarchy "cntl_log:I_cntl_log"
Info: Elaborating entity "portaout" for hierarchy "portaout:I_portaout"
Info: Elaborating entity "portain" for hierarchy "portain:I_portain"
Info: Elaborating entity "portbout" for hierarchy "portbout:I_portbout"
Info: Elaborating entity "portbin" for hierarchy "portbin:I_portbin"
Info: Elaborating entity "portcout" for hierarchy "portcout:I_portcout"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 243 device resources after synthesis - the final resource count might be different
    Info: Implemented 39 input pins
    Info: Implemented 42 output pins
    Info: Implemented 162 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
    Info: Allocated 162 megabytes of memory during processing
    Info: Processing ended: Thu Jun 12 18:18:40 2008
    Info: Elapsed time: 00:00:07