prev_cmp_a8255.map.qmsg

8255的vhdl代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 12 18:17:17 2008 " "Info: Processing started: Thu Jun 12 18:17:17 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A8255 -c A8255" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CNTL_LOG.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file CNTL_LOG.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 cntl_log-rtl " "Info: Found design unit 1: cntl_log-rtl" {  } { { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 32 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 cntl_log " "Info: Found entity 1: cntl_log" {  } { { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DOUT_MUX.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file DOUT_MUX.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dout_mux-rtl " "Info: Found design unit 1: dout_mux-rtl" {  } { { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 19 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 dout_mux " "Info: Found entity 1: dout_mux" {  } { { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PORTAIN.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file PORTAIN.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portain-rtl " "Info: Found design unit 1: portain-rtl" {  } { { "PORTAIN.VHD" "" { Text "E:/Study/A8255/PORTAIN.VHD" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 portain " "Info: Found entity 1: portain" {  } { { "PORTAIN.VHD" "" { Text "E:/Study/A8255/PORTAIN.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PORTAOUT.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file PORTAOUT.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portaout-rtl " "Info: Found design unit 1: portaout-rtl" {  } { { "PORTAOUT.VHD" "" { Text "E:/Study/A8255/PORTAOUT.VHD" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 portaout " "Info: Found entity 1: portaout" {  } { { "PORTAOUT.VHD" "" { Text "E:/Study/A8255/PORTAOUT.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PORTBIN.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file PORTBIN.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portbin-rtl " "Info: Found design unit 1: portbin-rtl" {  } { { "PORTBIN.VHD" "" { Text "E:/Study/A8255/PORTBIN.VHD" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 portbin " "Info: Found entity 1: portbin" {  } { { "PORTBIN.VHD" "" { Text "E:/Study/A8255/PORTBIN.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PORTBOUT.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file PORTBOUT.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portbout-rtl " "Info: Found design unit 1: portbout-rtl" {  } { { "PORTBOUT.VHD" "" { Text "E:/Study/A8255/PORTBOUT.VHD" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 portbout " "Info: Found entity 1: portbout" {  } { { "PORTBOUT.VHD" "" { Text "E:/Study/A8255/PORTBOUT.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PORTCOUT.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file PORTCOUT.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 portcout-rtl " "Info: Found design unit 1: portcout-rtl" {  } { { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 24 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 portcout " "Info: Found entity 1: portcout" {  } { { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "A8255.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file A8255.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 a8255-structure " "Info: Found design unit 1: a8255-structure" {  } { { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 29 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 a8255 " "Info: Found entity 1: a8255" {  } { { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "A8255 " "Info: Elaborating entity \"A8255\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dout_mux dout_mux:I_dout_mux " "Info: Elaborating entity \"dout_mux\" for hierarchy \"dout_mux:I_dout_mux\"" {  } { { "A8255.vhd" "I_dout_mux" { Text "E:/Study/A8255/A8255.vhd" 159 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_2050_UNCONVERTED" "DOUTSelect DOUT_MUX.VHD(22) " "Warning (10812): VHDL warning at DOUT_MUX.VHD(22): sensitivity list already contains DOUTSelect" {  } { { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 22 0 0 } }  } 0 10812 "VHDL warning at %2!s!: sensitivity list already contains %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntl_log cntl_log:I_cntl_log " "Info: Elaborating entity \"cntl_log\" for hierarchy \"cntl_log:I_cntl_log\"" {  } { { "A8255.vhd" "I_cntl_log" { Text "E:/Study/A8255/A8255.vhd" 171 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portaout portaout:I_portaout " "Info: Elaborating entity \"portaout\" for hierarchy \"portaout:I_portaout\"" {  } { { "A8255.vhd" "I_portaout" { Text "E:/Study/A8255/A8255.vhd" 196 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portain portain:I_portain " "Info: Elaborating entity \"portain\" for hierarchy \"portain:I_portain\"" {  } { { "A8255.vhd" "I_portain" { Text "E:/Study/A8255/A8255.vhd" 206 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portbout portbout:I_portbout " "Info: Elaborating entity \"portbout\" for hierarchy \"portbout:I_portbout\"" {  } { { "A8255.vhd" "I_portbout" { Text "E:/Study/A8255/A8255.vhd" 215 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portbin portbin:I_portbin " "Info: Elaborating entity \"portbin\" for hierarchy \"portbin:I_portbin\"" {  } { { "A8255.vhd" "I_portbin" { Text "E:/Study/A8255/A8255.vhd" 224 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "portcout portcout:I_portcout " "Info: Elaborating entity \"portcout\" for hierarchy \"portcout:I_portcout\"" {  } { { "A8255.vhd" "I_portcout" { Text "E:/Study/A8255/A8255.vhd" 233 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "268 " "Info: Implemented 268 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "39 " "Info: Implemented 39 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "42 " "Info: Implemented 42 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "187 " "Info: Implemented 187 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "161 " "Info: Allocated 161 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 18:17:24 2008 " "Info: Processing ended: Thu Jun 12 18:17:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}