a8255.tan.qmsg

8255的vhdl代码

{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DOUT\[4\] cntl_log:I_cntl_log\|ControlRegQ\[6\] 14.672 ns register " "Info: tco from clock \"CLK\" to destination pin \"DOUT\[4\]\" through register \"cntl_log:I_cntl_log\|ControlRegQ\[6\]\" is 14.672 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.778 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.666 ns) 2.778 ns cntl_log:I_cntl_log\|ControlRegQ\[6\] 3 REG LCFF_X25_Y7_N7 14 " "Info: 3: + IC(0.829 ns) + CELL(0.666 ns) = 2.778 ns; Loc. = LCFF_X25_Y7_N7; Fanout = 14; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK~clkctrl cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.01 % ) " "Info: Total cell delay = 1.806 ns ( 65.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.972 ns ( 34.99 % ) " "Info: Total interconnect delay = 0.972 ns ( 34.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cntl_log:I_cntl_log|ControlRegQ[6] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.590 ns + Longest register pin " "Info: + Longest register to pin delay is 11.590 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cntl_log:I_cntl_log\|ControlRegQ\[6\] 1 REG LCFF_X25_Y7_N7 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y7_N7; Fanout = 14; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[6\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.450 ns) + CELL(0.206 ns) 0.656 ns cntl_log:I_cntl_log\|Equal2~21 2 COMB LCCOMB_X25_Y7_N16 7 " "Info: 2: + IC(0.450 ns) + CELL(0.206 ns) = 0.656 ns; Loc. = LCCOMB_X25_Y7_N16; Fanout = 7; COMB Node = 'cntl_log:I_cntl_log\|Equal2~21'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.656 ns" { cntl_log:I_cntl_log|ControlRegQ[6] cntl_log:I_cntl_log|Equal2~21 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.624 ns) 1.989 ns cntl_log:I_cntl_log\|Mux0~72 3 COMB LCCOMB_X26_Y7_N4 12 " "Info: 3: + IC(0.709 ns) + CELL(0.624 ns) = 1.989 ns; Loc. = LCCOMB_X26_Y7_N4; Fanout = 12; COMB Node = 'cntl_log:I_cntl_log\|Mux0~72'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.333 ns" { cntl_log:I_cntl_log|Equal2~21 cntl_log:I_cntl_log|Mux0~72 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.589 ns) 3.731 ns dout_mux:I_dout_mux\|Mux3~527 4 COMB LCCOMB_X25_Y8_N6 1 " "Info: 4: + IC(1.153 ns) + CELL(0.589 ns) = 3.731 ns; Loc. = LCCOMB_X25_Y8_N6; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~527'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux3~527 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.651 ns) 4.781 ns dout_mux:I_dout_mux\|Mux3~528 5 COMB LCCOMB_X25_Y8_N16 1 " "Info: 5: + IC(0.399 ns) + CELL(0.651 ns) = 4.781 ns; Loc. = LCCOMB_X25_Y8_N16; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~528'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.050 ns" { dout_mux:I_dout_mux|Mux3~527 dout_mux:I_dout_mux|Mux3~528 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.366 ns) 5.892 ns dout_mux:I_dout_mux\|Mux3~529 6 COMB LCCOMB_X24_Y8_N4 1 " "Info: 6: + IC(0.745 ns) + CELL(0.366 ns) = 5.892 ns; Loc. = LCCOMB_X24_Y8_N4; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~529'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.111 ns" { dout_mux:I_dout_mux|Mux3~528 dout_mux:I_dout_mux|Mux3~529 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.442 ns) + CELL(3.256 ns) 11.590 ns DOUT\[4\] 7 PIN PIN_185 0 " "Info: 7: + IC(2.442 ns) + CELL(3.256 ns) = 11.590 ns; Loc. = PIN_185; Fanout = 0; PIN Node = 'DOUT\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.698 ns" { dout_mux:I_dout_mux|Mux3~529 DOUT[4] } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.692 ns ( 49.11 % ) " "Info: Total cell delay = 5.692 ns ( 49.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.898 ns ( 50.89 % ) " "Info: Total interconnect delay = 5.898 ns ( 50.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.590 ns" { cntl_log:I_cntl_log|ControlRegQ[6] cntl_log:I_cntl_log|Equal2~21 cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux3~527 dout_mux:I_dout_mux|Mux3~528 dout_mux:I_dout_mux|Mux3~529 DOUT[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.590 ns" { cntl_log:I_cntl_log|ControlRegQ[6] {} cntl_log:I_cntl_log|Equal2~21 {} cntl_log:I_cntl_log|Mux0~72 {} dout_mux:I_dout_mux|Mux3~527 {} dout_mux:I_dout_mux|Mux3~528 {} dout_mux:I_dout_mux|Mux3~529 {} DOUT[4] {} } { 0.000ns 0.450ns 0.709ns 1.153ns 0.399ns 0.745ns 2.442ns } { 0.000ns 0.206ns 0.624ns 0.589ns 0.651ns 0.366ns 3.256ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl cntl_log:I_cntl_log|ControlRegQ[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} cntl_log:I_cntl_log|ControlRegQ[6] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.590 ns" { cntl_log:I_cntl_log|ControlRegQ[6] cntl_log:I_cntl_log|Equal2~21 cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux3~527 dout_mux:I_dout_mux|Mux3~528 dout_mux:I_dout_mux|Mux3~529 DOUT[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.590 ns" { cntl_log:I_cntl_log|ControlRegQ[6] {} cntl_log:I_cntl_log|Equal2~21 {} cntl_log:I_cntl_log|Mux0~72 {} dout_mux:I_dout_mux|Mux3~527 {} dout_mux:I_dout_mux|Mux3~528 {} dout_mux:I_dout_mux|Mux3~529 {} DOUT[4] {} } { 0.000ns 0.450ns 0.709ns 1.153ns 0.399ns 0.745ns 2.442ns } { 0.000ns 0.206ns 0.624ns 0.589ns 0.651ns 0.366ns 3.256ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A\[0\] DOUT\[4\] 17.310 ns Longest " "Info: Longest tpd from source pin \"A\[0\]\" to destination pin \"DOUT\[4\]\" is 17.310 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns A\[0\] 1 PIN PIN_128 29 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_128; Fanout = 29; PIN Node = 'A\[0\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { A[0] } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.073 ns) + CELL(0.651 ns) 7.709 ns cntl_log:I_cntl_log\|Mux0~72 2 COMB LCCOMB_X26_Y7_N4 12 " "Info: 2: + IC(6.073 ns) + CELL(0.651 ns) = 7.709 ns; Loc. = LCCOMB_X26_Y7_N4; Fanout = 12; COMB Node = 'cntl_log:I_cntl_log\|Mux0~72'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.724 ns" { A[0] cntl_log:I_cntl_log|Mux0~72 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.589 ns) 9.451 ns dout_mux:I_dout_mux\|Mux3~527 3 COMB LCCOMB_X25_Y8_N6 1 " "Info: 3: + IC(1.153 ns) + CELL(0.589 ns) = 9.451 ns; Loc. = LCCOMB_X25_Y8_N6; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~527'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux3~527 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.651 ns) 10.501 ns dout_mux:I_dout_mux\|Mux3~528 4 COMB LCCOMB_X25_Y8_N16 1 " "Info: 4: + IC(0.399 ns) + CELL(0.651 ns) = 10.501 ns; Loc. = LCCOMB_X25_Y8_N16; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~528'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.050 ns" { dout_mux:I_dout_mux|Mux3~527 dout_mux:I_dout_mux|Mux3~528 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.366 ns) 11.612 ns dout_mux:I_dout_mux\|Mux3~529 5 COMB LCCOMB_X24_Y8_N4 1 " "Info: 5: + IC(0.745 ns) + CELL(0.366 ns) = 11.612 ns; Loc. = LCCOMB_X24_Y8_N4; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux3~529'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.111 ns" { dout_mux:I_dout_mux|Mux3~528 dout_mux:I_dout_mux|Mux3~529 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.442 ns) + CELL(3.256 ns) 17.310 ns DOUT\[4\] 6 PIN PIN_185 0 " "Info: 6: + IC(2.442 ns) + CELL(3.256 ns) = 17.310 ns; Loc. = PIN_185; Fanout = 0; PIN Node = 'DOUT\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.698 ns" { dout_mux:I_dout_mux|Mux3~529 DOUT[4] } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.498 ns ( 37.54 % ) " "Info: Total cell delay = 6.498 ns ( 37.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.812 ns ( 62.46 % ) " "Info: Total interconnect delay = 10.812 ns ( 62.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.310 ns" { A[0] cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux3~527 dout_mux:I_dout_mux|Mux3~528 dout_mux:I_dout_mux|Mux3~529 DOUT[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.310 ns" { A[0] {} A[0]~combout {} cntl_log:I_cntl_log|Mux0~72 {} dout_mux:I_dout_mux|Mux3~527 {} dout_mux:I_dout_mux|Mux3~528 {} dout_mux:I_dout_mux|Mux3~529 {} DOUT[4] {} } { 0.000ns 0.000ns 6.073ns 1.153ns 0.399ns 0.745ns 2.442ns } { 0.000ns 0.985ns 0.651ns 0.589ns 0.651ns 0.366ns 3.256ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "portbin:I_portbin\|PortBInRegQ\[1\] PBIN\[1\] CLK -0.682 ns register " "Info: th for register \"portbin:I_portbin\|PortBInRegQ\[1\]\" (data pin = \"PBIN\[1\]\", clock pin = \"CLK\") is -0.682 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.791 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 2.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.666 ns) 2.791 ns portbin:I_portbin\|PortBInRegQ\[1\] 3 REG LCFF_X24_Y8_N19 1 " "Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.791 ns; Loc. = LCFF_X24_Y8_N19; Fanout = 1; REG Node = 'portbin:I_portbin\|PortBInRegQ\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { CLK~clkctrl portbin:I_portbin|PortBInRegQ[1] } "NODE_NAME" } } { "PORTBIN.VHD" "" { Text "E:/Study/A8255/PORTBIN.VHD" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.71 % ) " "Info: Total cell delay = 1.806 ns ( 64.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.985 ns ( 35.29 % ) " "Info: Total interconnect delay = 0.985 ns ( 35.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { CLK CLK~clkctrl portbin:I_portbin|PortBInRegQ[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portbin:I_portbin|PortBInRegQ[1] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "PORTBIN.VHD" "" { Text "E:/Study/A8255/PORTBIN.VHD" 43 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.779 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns PBIN\[1\] 1 PIN PIN_28 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_28; Fanout = 2; PIN Node = 'PBIN\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PBIN[1] } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.179 ns) + CELL(0.460 ns) 3.779 ns portbin:I_portbin\|PortBInRegQ\[1\] 2 REG LCFF_X24_Y8_N19 1 " "Info: 2: + IC(2.179 ns) + CELL(0.460 ns) = 3.779 ns; Loc. = LCFF_X24_Y8_N19; Fanout = 1; REG Node = 'portbin:I_portbin\|PortBInRegQ\[1\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.639 ns" { PBIN[1] portbin:I_portbin|PortBInRegQ[1] } "NODE_NAME" } } { "PORTBIN.VHD" "" { Text "E:/Study/A8255/PORTBIN.VHD" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.600 ns ( 42.34 % ) " "Info: Total cell delay = 1.600 ns ( 42.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.179 ns ( 57.66 % ) " "Info: Total interconnect delay = 2.179 ns ( 57.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.779 ns" { PBIN[1] portbin:I_portbin|PortBInRegQ[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.779 ns" { PBIN[1] {} PBIN[1]~combout {} portbin:I_portbin|PortBInRegQ[1] {} } { 0.000ns 0.000ns 2.179ns } { 0.000ns 1.140ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { CLK CLK~clkctrl portbin:I_portbin|PortBInRegQ[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portbin:I_portbin|PortBInRegQ[1] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.779 ns" { PBIN[1] portbin:I_portbin|PortBInRegQ[1] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.779 ns" { PBIN[1] {} PBIN[1]~combout {} portbin:I_portbin|PortBInRegQ[1] {} } { 0.000ns 0.000ns 2.179ns } { 0.000ns 1.140ns 0.460ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}