a8255.tan.qmsg

8255的vhdl代码

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register portcout:I_portcout\|PortCOutRegQ\[5\] register portcout:I_portcout\|PortCOutRegQ\[3\] 210.08 MHz 4.76 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 210.08 MHz between source register \"portcout:I_portcout\|PortCOutRegQ\[5\]\" and destination register \"portcout:I_portcout\|PortCOutRegQ\[3\]\" (period= 4.76 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.496 ns + Longest register register " "Info: + Longest register to register delay is 4.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns portcout:I_portcout\|PortCOutRegQ\[5\] 1 REG LCFF_X24_Y7_N19 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y7_N19; Fanout = 5; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.765 ns) + CELL(0.206 ns) 0.971 ns portcout:I_portcout\|PortCDataProc~222 2 COMB LCCOMB_X25_Y7_N30 2 " "Info: 2: + IC(0.765 ns) + CELL(0.206 ns) = 0.971 ns; Loc. = LCCOMB_X25_Y7_N30; Fanout = 2; COMB Node = 'portcout:I_portcout\|PortCDataProc~222'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.971 ns" { portcout:I_portcout|PortCOutRegQ[5] portcout:I_portcout|PortCDataProc~222 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.614 ns) + CELL(0.370 ns) 1.955 ns portcout:I_portcout\|PortCOutRegD~6519 3 COMB LCCOMB_X26_Y7_N0 1 " "Info: 3: + IC(0.614 ns) + CELL(0.370 ns) = 1.955 ns; Loc. = LCCOMB_X26_Y7_N0; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD~6519'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.984 ns" { portcout:I_portcout|PortCDataProc~222 portcout:I_portcout|PortCOutRegD~6519 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.350 ns) + CELL(0.206 ns) 2.511 ns portcout:I_portcout\|PortCOutRegD\[3\]~6520 4 COMB LCCOMB_X26_Y7_N2 1 " "Info: 4: + IC(0.350 ns) + CELL(0.206 ns) = 2.511 ns; Loc. = LCCOMB_X26_Y7_N2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6520'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.556 ns" { portcout:I_portcout|PortCOutRegD~6519 portcout:I_portcout|PortCOutRegD[3]~6520 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.206 ns) 3.086 ns portcout:I_portcout\|PortCOutRegD\[3\]~6521 5 COMB LCCOMB_X26_Y7_N18 1 " "Info: 5: + IC(0.369 ns) + CELL(0.206 ns) = 3.086 ns; Loc. = LCCOMB_X26_Y7_N18; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6521'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.575 ns" { portcout:I_portcout|PortCOutRegD[3]~6520 portcout:I_portcout|PortCOutRegD[3]~6521 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 3.655 ns portcout:I_portcout\|PortCOutRegD\[3\]~6524 6 COMB LCCOMB_X26_Y7_N20 1 " "Info: 6: + IC(0.363 ns) + CELL(0.206 ns) = 3.655 ns; Loc. = LCCOMB_X26_Y7_N20; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6524'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { portcout:I_portcout|PortCOutRegD[3]~6521 portcout:I_portcout|PortCOutRegD[3]~6524 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.460 ns) 4.496 ns portcout:I_portcout\|PortCOutRegQ\[3\] 7 REG LCFF_X26_Y7_N31 5 " "Info: 7: + IC(0.381 ns) + CELL(0.460 ns) = 4.496 ns; Loc. = LCFF_X26_Y7_N31; Fanout = 5; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.841 ns" { portcout:I_portcout|PortCOutRegD[3]~6524 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.654 ns ( 36.79 % ) " "Info: Total cell delay = 1.654 ns ( 36.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.842 ns ( 63.21 % ) " "Info: Total interconnect delay = 2.842 ns ( 63.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.496 ns" { portcout:I_portcout|PortCOutRegQ[5] portcout:I_portcout|PortCDataProc~222 portcout:I_portcout|PortCOutRegD~6519 portcout:I_portcout|PortCOutRegD[3]~6520 portcout:I_portcout|PortCOutRegD[3]~6521 portcout:I_portcout|PortCOutRegD[3]~6524 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.496 ns" { portcout:I_portcout|PortCOutRegQ[5] {} portcout:I_portcout|PortCDataProc~222 {} portcout:I_portcout|PortCOutRegD~6519 {} portcout:I_portcout|PortCOutRegD[3]~6520 {} portcout:I_portcout|PortCOutRegD[3]~6521 {} portcout:I_portcout|PortCOutRegD[3]~6524 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.765ns 0.614ns 0.350ns 0.369ns 0.363ns 0.381ns } { 0.000ns 0.206ns 0.370ns 0.206ns 0.206ns 0.206ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.778 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.666 ns) 2.778 ns portcout:I_portcout\|PortCOutRegQ\[3\] 3 REG LCFF_X26_Y7_N31 5 " "Info: 3: + IC(0.829 ns) + CELL(0.666 ns) = 2.778 ns; Loc. = LCFF_X26_Y7_N31; Fanout = 5; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK~clkctrl portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.01 % ) " "Info: Total cell delay = 1.806 ns ( 65.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.972 ns ( 34.99 % ) " "Info: Total interconnect delay = 0.972 ns ( 34.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.778 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.666 ns) 2.778 ns portcout:I_portcout\|PortCOutRegQ\[5\] 3 REG LCFF_X24_Y7_N19 5 " "Info: 3: + IC(0.829 ns) + CELL(0.666 ns) = 2.778 ns; Loc. = LCFF_X24_Y7_N19; Fanout = 5; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[5\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK~clkctrl portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.01 % ) " "Info: Total cell delay = 1.806 ns ( 65.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.972 ns ( 34.99 % ) " "Info: Total interconnect delay = 0.972 ns ( 34.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portcout:I_portcout|PortCOutRegQ[5] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portcout:I_portcout|PortCOutRegQ[5] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.496 ns" { portcout:I_portcout|PortCOutRegQ[5] portcout:I_portcout|PortCDataProc~222 portcout:I_portcout|PortCOutRegD~6519 portcout:I_portcout|PortCOutRegD[3]~6520 portcout:I_portcout|PortCOutRegD[3]~6521 portcout:I_portcout|PortCOutRegD[3]~6524 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.496 ns" { portcout:I_portcout|PortCOutRegQ[5] {} portcout:I_portcout|PortCDataProc~222 {} portcout:I_portcout|PortCOutRegD~6519 {} portcout:I_portcout|PortCOutRegD[3]~6520 {} portcout:I_portcout|PortCOutRegD[3]~6521 {} portcout:I_portcout|PortCOutRegD[3]~6524 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.765ns 0.614ns 0.350ns 0.369ns 0.363ns 0.381ns } { 0.000ns 0.206ns 0.370ns 0.206ns 0.206ns 0.206ns 0.460ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl portcout:I_portcout|PortCOutRegQ[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portcout:I_portcout|PortCOutRegQ[5] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "portcout:I_portcout\|PortCOutRegQ\[3\] nWR CLK 11.357 ns register " "Info: tsu for register \"portcout:I_portcout\|PortCOutRegQ\[3\]\" (data pin = \"nWR\", clock pin = \"CLK\") is 11.357 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.175 ns + Longest pin register " "Info: + Longest pin to register delay is 14.175 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns nWR 1 PIN PIN_161 5 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_161; Fanout = 5; PIN Node = 'nWR'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { nWR } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.004 ns) + CELL(0.370 ns) 8.368 ns cntl_log:I_cntl_log\|PortAOutLd~1 2 COMB LCCOMB_X24_Y7_N8 13 " "Info: 2: + IC(7.004 ns) + CELL(0.370 ns) = 8.368 ns; Loc. = LCCOMB_X24_Y7_N8; Fanout = 13; COMB Node = 'cntl_log:I_cntl_log\|PortAOutLd~1'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.374 ns" { nWR cntl_log:I_cntl_log|PortAOutLd~1 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.425 ns) + CELL(0.647 ns) 11.440 ns portcout:I_portcout\|PortCOutRegD\[3\]~6516 3 COMB LCCOMB_X26_Y7_N8 1 " "Info: 3: + IC(2.425 ns) + CELL(0.647 ns) = 11.440 ns; Loc. = LCCOMB_X26_Y7_N8; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6516'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.072 ns" { cntl_log:I_cntl_log|PortAOutLd~1 portcout:I_portcout|PortCOutRegD[3]~6516 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.380 ns) + CELL(0.370 ns) 12.190 ns portcout:I_portcout\|PortCOutRegD\[3\]~6520 4 COMB LCCOMB_X26_Y7_N2 1 " "Info: 4: + IC(0.380 ns) + CELL(0.370 ns) = 12.190 ns; Loc. = LCCOMB_X26_Y7_N2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6520'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.750 ns" { portcout:I_portcout|PortCOutRegD[3]~6516 portcout:I_portcout|PortCOutRegD[3]~6520 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.206 ns) 12.765 ns portcout:I_portcout\|PortCOutRegD\[3\]~6521 5 COMB LCCOMB_X26_Y7_N18 1 " "Info: 5: + IC(0.369 ns) + CELL(0.206 ns) = 12.765 ns; Loc. = LCCOMB_X26_Y7_N18; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6521'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.575 ns" { portcout:I_portcout|PortCOutRegD[3]~6520 portcout:I_portcout|PortCOutRegD[3]~6521 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.363 ns) + CELL(0.206 ns) 13.334 ns portcout:I_portcout\|PortCOutRegD\[3\]~6524 6 COMB LCCOMB_X26_Y7_N20 1 " "Info: 6: + IC(0.363 ns) + CELL(0.206 ns) = 13.334 ns; Loc. = LCCOMB_X26_Y7_N20; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6524'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.569 ns" { portcout:I_portcout|PortCOutRegD[3]~6521 portcout:I_portcout|PortCOutRegD[3]~6524 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.381 ns) + CELL(0.460 ns) 14.175 ns portcout:I_portcout\|PortCOutRegQ\[3\] 7 REG LCFF_X26_Y7_N31 5 " "Info: 7: + IC(0.381 ns) + CELL(0.460 ns) = 14.175 ns; Loc. = LCFF_X26_Y7_N31; Fanout = 5; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.841 ns" { portcout:I_portcout|PortCOutRegD[3]~6524 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.253 ns ( 22.95 % ) " "Info: Total cell delay = 3.253 ns ( 22.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.922 ns ( 77.05 % ) " "Info: Total interconnect delay = 10.922 ns ( 77.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.175 ns" { nWR cntl_log:I_cntl_log|PortAOutLd~1 portcout:I_portcout|PortCOutRegD[3]~6516 portcout:I_portcout|PortCOutRegD[3]~6520 portcout:I_portcout|PortCOutRegD[3]~6521 portcout:I_portcout|PortCOutRegD[3]~6524 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.175 ns" { nWR {} nWR~combout {} cntl_log:I_cntl_log|PortAOutLd~1 {} portcout:I_portcout|PortCOutRegD[3]~6516 {} portcout:I_portcout|PortCOutRegD[3]~6520 {} portcout:I_portcout|PortCOutRegD[3]~6521 {} portcout:I_portcout|PortCOutRegD[3]~6524 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 7.004ns 2.425ns 0.380ns 0.369ns 0.363ns 0.381ns } { 0.000ns 0.994ns 0.370ns 0.647ns 0.370ns 0.206ns 0.206ns 0.460ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 2.778 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 2.778 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 54 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 54; COMB Node = 'CLK~clkctrl'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.829 ns) + CELL(0.666 ns) 2.778 ns portcout:I_portcout\|PortCOutRegQ\[3\] 3 REG LCFF_X26_Y7_N31 5 " "Info: 3: + IC(0.829 ns) + CELL(0.666 ns) = 2.778 ns; Loc. = LCFF_X26_Y7_N31; Fanout = 5; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.495 ns" { CLK~clkctrl portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 65.01 % ) " "Info: Total cell delay = 1.806 ns ( 65.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.972 ns ( 34.99 % ) " "Info: Total interconnect delay = 0.972 ns ( 34.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.175 ns" { nWR cntl_log:I_cntl_log|PortAOutLd~1 portcout:I_portcout|PortCOutRegD[3]~6516 portcout:I_portcout|PortCOutRegD[3]~6520 portcout:I_portcout|PortCOutRegD[3]~6521 portcout:I_portcout|PortCOutRegD[3]~6524 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.175 ns" { nWR {} nWR~combout {} cntl_log:I_cntl_log|PortAOutLd~1 {} portcout:I_portcout|PortCOutRegD[3]~6516 {} portcout:I_portcout|PortCOutRegD[3]~6520 {} portcout:I_portcout|PortCOutRegD[3]~6521 {} portcout:I_portcout|PortCOutRegD[3]~6524 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 7.004ns 2.425ns 0.380ns 0.369ns 0.363ns 0.381ns } { 0.000ns 0.994ns 0.370ns 0.647ns 0.370ns 0.206ns 0.206ns 0.460ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.778 ns" { CLK CLK~clkctrl portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.778 ns" { CLK {} CLK~combout {} CLK~clkctrl {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 0.143ns 0.829ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}