prev_cmp_a8255.tan.qmsg

8255的vhdl代码

{ "Info" "ITDB_TH_RESULT" "portain:I_portain\|PortAInRegQ\[4\] PAIN\[4\] CLK -2.354 ns register " "Info: th for register \"portain:I_portain\|PortAInRegQ\[4\]\" (data pin = \"PAIN\[4\]\", clock pin = \"CLK\") is -2.354 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.663 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns portain:I_portain\|PortAInRegQ\[4\] 2 REG LC10_1_E2 1 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC10_1_E2; Fanout = 1; REG Node = 'portain:I_portain\|PortAInRegQ\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.773 ns" { CLK portain:I_portain|PortAInRegQ[4] } "NODE_NAME" } } { "PORTAIN.VHD" "" { Text "E:/Study/A8255/PORTAIN.VHD" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { CLK portain:I_portain|PortAInRegQ[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { CLK {} CLK~out0 {} portain:I_portain|PortAInRegQ[4] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.364 ns + " "Info: + Micro hold delay of destination is 0.364 ns" {  } { { "PORTAIN.VHD" "" { Text "E:/Study/A8255/PORTAIN.VHD" 43 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.381 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.381 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns PAIN\[4\] 1 PIN PIN_27 2 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_27; Fanout = 2; PIN Node = 'PAIN\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { PAIN[4] } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.062 ns) + CELL(0.079 ns) 4.381 ns portain:I_portain\|PortAInRegQ\[4\] 2 REG LC10_1_E2 1 " "Info: 2: + IC(3.062 ns) + CELL(0.079 ns) = 4.381 ns; Loc. = LC10_1_E2; Fanout = 1; REG Node = 'portain:I_portain\|PortAInRegQ\[4\]'" {  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.141 ns" { PAIN[4] portain:I_portain|PortAInRegQ[4] } "NODE_NAME" } } { "PORTAIN.VHD" "" { Text "E:/Study/A8255/PORTAIN.VHD" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.319 ns ( 30.11 % ) " "Info: Total cell delay = 1.319 ns ( 30.11 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.062 ns ( 69.89 % ) " "Info: Total interconnect delay = 3.062 ns ( 69.89 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.381 ns" { PAIN[4] portain:I_portain|PortAInRegQ[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.381 ns" { PAIN[4] {} PAIN[4]~out0 {} portain:I_portain|PortAInRegQ[4] {} } { 0.000ns 0.000ns 3.062ns } { 0.000ns 1.240ns 0.079ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { CLK portain:I_portain|PortAInRegQ[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { CLK {} CLK~out0 {} portain:I_portain|PortAInRegQ[4] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.381 ns" { PAIN[4] portain:I_portain|PortAInRegQ[4] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.381 ns" { PAIN[4] {} PAIN[4]~out0 {} portain:I_portain|PortAInRegQ[4] {} } { 0.000ns 0.000ns 3.062ns } { 0.000ns 1.240ns 0.079ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "118 " "Info: Allocated 118 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 12 18:17:39 2008 " "Info: Processing ended: Thu Jun 12 18:17:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}