📄 prev_cmp_a8255.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" { } { { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } } { "d:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register cntl_log:I_cntl_log\|ControlRegQ\[2\] register portcout:I_portcout\|PortCOutRegQ\[3\] 171.41 MHz 5.834 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 171.41 MHz between source register \"cntl_log:I_cntl_log\|ControlRegQ\[2\]\" and destination register \"portcout:I_portcout\|PortCOutRegQ\[3\]\" (period= 5.834 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.311 ns + Longest register register " "Info: + Longest register to register delay is 5.311 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns cntl_log:I_cntl_log\|ControlRegQ\[2\] 1 REG LC5_9_C2 19 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC5_9_C2; Fanout = 19; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[2\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cntl_log:I_cntl_log|ControlRegQ[2] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.736 ns) + CELL(0.161 ns) 2.058 ns portcout:I_portcout\|PortCDataProc~183 2 COMB LC2_6_A2 1 " "Info: 2: + IC(1.736 ns) + CELL(0.161 ns) = 2.058 ns; Loc. = LC2_6_A2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCDataProc~183'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.897 ns" { cntl_log:I_cntl_log|ControlRegQ[2] portcout:I_portcout|PortCDataProc~183 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.532 ns) 2.590 ns portcout:I_portcout\|PortCOutRegD\[3\]~6751 3 COMB LC3_6_A2 1 " "Info: 3: + IC(0.000 ns) + CELL(0.532 ns) = 2.590 ns; Loc. = LC3_6_A2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6751'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.532 ns" { portcout:I_portcout|PortCDataProc~183 portcout:I_portcout|PortCOutRegD[3]~6751 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.879 ns) 3.722 ns portcout:I_portcout\|PortCOutRegD\[3\]~6705 4 COMB LC4_6_A2 1 " "Info: 4: + IC(0.253 ns) + CELL(0.879 ns) = 3.722 ns; Loc. = LC4_6_A2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[3\]~6705'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.132 ns" { portcout:I_portcout|PortCOutRegD[3]~6751 portcout:I_portcout|PortCOutRegD[3]~6705 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.058 ns) + CELL(0.531 ns) 5.311 ns portcout:I_portcout\|PortCOutRegQ\[3\] 5 REG LC1_3_A2 7 " "Info: 5: + IC(1.058 ns) + CELL(0.531 ns) = 5.311 ns; Loc. = LC1_3_A2; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.589 ns" { portcout:I_portcout|PortCOutRegD[3]~6705 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.264 ns ( 42.63 % ) " "Info: Total cell delay = 2.264 ns ( 42.63 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.047 ns ( 57.37 % ) " "Info: Total interconnect delay = 3.047 ns ( 57.37 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.311 ns" { cntl_log:I_cntl_log|ControlRegQ[2] portcout:I_portcout|PortCDataProc~183 portcout:I_portcout|PortCOutRegD[3]~6751 portcout:I_portcout|PortCOutRegD[3]~6705 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.311 ns" { cntl_log:I_cntl_log|ControlRegQ[2] {} portcout:I_portcout|PortCDataProc~183 {} portcout:I_portcout|PortCOutRegD[3]~6751 {} portcout:I_portcout|PortCOutRegD[3]~6705 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 1.736ns 0.000ns 0.253ns 1.058ns } { 0.161ns 0.161ns 0.532ns 0.879ns 0.531ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.010 ns - Smallest " "Info: - Smallest clock skew is 0.010 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.673 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns portcout:I_portcout\|PortCOutRegQ\[3\] 2 REG LC1_3_A2 7 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC1_3_A2; Fanout = 7; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[3\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { CLK {} CLK~out0 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.663 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 1.663 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.773 ns) + CELL(0.000 ns) 1.663 ns cntl_log:I_cntl_log\|ControlRegQ\[2\] 2 REG LC5_9_C2 19 " "Info: 2: + IC(0.773 ns) + CELL(0.000 ns) = 1.663 ns; Loc. = LC5_9_C2; Fanout = 19; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[2\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.773 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[2] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.52 % ) " "Info: Total cell delay = 0.890 ns ( 53.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.773 ns ( 46.48 % ) " "Info: Total interconnect delay = 0.773 ns ( 46.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { CLK {} CLK~out0 {} cntl_log:I_cntl_log|ControlRegQ[2] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { CLK {} CLK~out0 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { CLK {} CLK~out0 {} cntl_log:I_cntl_log|ControlRegQ[2] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" { } { { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" { } { { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.311 ns" { cntl_log:I_cntl_log|ControlRegQ[2] portcout:I_portcout|PortCDataProc~183 portcout:I_portcout|PortCOutRegD[3]~6751 portcout:I_portcout|PortCOutRegD[3]~6705 portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.311 ns" { cntl_log:I_cntl_log|ControlRegQ[2] {} portcout:I_portcout|PortCDataProc~183 {} portcout:I_portcout|PortCOutRegD[3]~6751 {} portcout:I_portcout|PortCOutRegD[3]~6705 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 1.736ns 0.000ns 0.253ns 1.058ns } { 0.161ns 0.161ns 0.532ns 0.879ns 0.531ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[3] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { CLK {} CLK~out0 {} portcout:I_portcout|PortCOutRegQ[3] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.663 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[2] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.663 ns" { CLK {} CLK~out0 {} cntl_log:I_cntl_log|ControlRegQ[2] {} } { 0.000ns 0.000ns 0.773ns } { 0.000ns 0.890ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "portcout:I_portcout\|PortCOutRegQ\[7\] nCS CLK 12.652 ns register " "Info: tsu for register \"portcout:I_portcout\|PortCOutRegQ\[7\]\" (data pin = \"nCS\", clock pin = \"CLK\") is 12.652 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.127 ns + Longest pin register " "Info: + Longest pin to register delay is 14.127 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns nCS 1 PIN PIN_97 17 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_97; Fanout = 17; PIN Node = 'nCS'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { nCS } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.374 ns) + CELL(0.879 ns) 7.493 ns cntl_log:I_cntl_log\|ControlLogicProc~67 2 COMB LC2_7_A2 14 " "Info: 2: + IC(5.374 ns) + CELL(0.879 ns) = 7.493 ns; Loc. = LC2_7_A2; Fanout = 14; COMB Node = 'cntl_log:I_cntl_log\|ControlLogicProc~67'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.253 ns" { nCS cntl_log:I_cntl_log|ControlLogicProc~67 } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.114 ns) + CELL(0.890 ns) 9.497 ns cntl_log:I_cntl_log\|PortCOutLd\[7\]~806 3 COMB LC4_9_A2 2 " "Info: 3: + IC(1.114 ns) + CELL(0.890 ns) = 9.497 ns; Loc. = LC4_9_A2; Fanout = 2; COMB Node = 'cntl_log:I_cntl_log\|PortCOutLd\[7\]~806'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.004 ns" { cntl_log:I_cntl_log|ControlLogicProc~67 cntl_log:I_cntl_log|PortCOutLd[7]~806 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.079 ns) + CELL(0.879 ns) 11.455 ns cntl_log:I_cntl_log\|PortCOutLd\[7\]~808 4 COMB LC6_5_A2 2 " "Info: 4: + IC(1.079 ns) + CELL(0.879 ns) = 11.455 ns; Loc. = LC6_5_A2; Fanout = 2; COMB Node = 'cntl_log:I_cntl_log\|PortCOutLd\[7\]~808'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.958 ns" { cntl_log:I_cntl_log|PortCOutLd[7]~806 cntl_log:I_cntl_log|PortCOutLd[7]~808 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.879 ns) 13.329 ns portcout:I_portcout\|PortCOutRegD\[7\]~6724 5 COMB LC2_1_A2 1 " "Info: 5: + IC(0.995 ns) + CELL(0.879 ns) = 13.329 ns; Loc. = LC2_1_A2; Fanout = 1; COMB Node = 'portcout:I_portcout\|PortCOutRegD\[7\]~6724'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.874 ns" { cntl_log:I_cntl_log|PortCOutLd[7]~808 portcout:I_portcout|PortCOutRegD[7]~6724 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 26 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.531 ns) 14.127 ns portcout:I_portcout\|PortCOutRegQ\[7\] 6 REG LC9_2_A2 6 " "Info: 6: + IC(0.267 ns) + CELL(0.531 ns) = 14.127 ns; Loc. = LC9_2_A2; Fanout = 6; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[7\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.798 ns" { portcout:I_portcout|PortCOutRegD[7]~6724 portcout:I_portcout|PortCOutRegQ[7] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.298 ns ( 37.50 % ) " "Info: Total cell delay = 5.298 ns ( 37.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.829 ns ( 62.50 % ) " "Info: Total interconnect delay = 8.829 ns ( 62.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.127 ns" { nCS cntl_log:I_cntl_log|ControlLogicProc~67 cntl_log:I_cntl_log|PortCOutLd[7]~806 cntl_log:I_cntl_log|PortCOutLd[7]~808 portcout:I_portcout|PortCOutRegD[7]~6724 portcout:I_portcout|PortCOutRegQ[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.127 ns" { nCS {} nCS~out0 {} cntl_log:I_cntl_log|ControlLogicProc~67 {} cntl_log:I_cntl_log|PortCOutLd[7]~806 {} cntl_log:I_cntl_log|PortCOutLd[7]~808 {} portcout:I_portcout|PortCOutRegD[7]~6724 {} portcout:I_portcout|PortCOutRegQ[7] {} } { 0.000ns 0.000ns 5.374ns 1.114ns 1.079ns 0.995ns 0.267ns } { 0.000ns 1.240ns 0.879ns 0.890ns 0.879ns 0.879ns 0.531ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.198 ns + " "Info: + Micro setup delay of destination is 0.198 ns" { } { { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 1.673 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns portcout:I_portcout\|PortCOutRegQ\[7\] 2 REG LC9_2_A2 6 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC9_2_A2; Fanout = 6; REG Node = 'portcout:I_portcout\|PortCOutRegQ\[7\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { CLK portcout:I_portcout|PortCOutRegQ[7] } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { CLK {} CLK~out0 {} portcout:I_portcout|PortCOutRegQ[7] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.127 ns" { nCS cntl_log:I_cntl_log|ControlLogicProc~67 cntl_log:I_cntl_log|PortCOutLd[7]~806 cntl_log:I_cntl_log|PortCOutLd[7]~808 portcout:I_portcout|PortCOutRegD[7]~6724 portcout:I_portcout|PortCOutRegQ[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.127 ns" { nCS {} nCS~out0 {} cntl_log:I_cntl_log|ControlLogicProc~67 {} cntl_log:I_cntl_log|PortCOutLd[7]~806 {} cntl_log:I_cntl_log|PortCOutLd[7]~808 {} portcout:I_portcout|PortCOutRegD[7]~6724 {} portcout:I_portcout|PortCOutRegQ[7] {} } { 0.000ns 0.000ns 5.374ns 1.114ns 1.079ns 0.995ns 0.267ns } { 0.000ns 1.240ns 0.879ns 0.890ns 0.879ns 0.879ns 0.531ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK portcout:I_portcout|PortCOutRegQ[7] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { CLK {} CLK~out0 {} portcout:I_portcout|PortCOutRegQ[7] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK DOUT\[6\] cntl_log:I_cntl_log\|ControlRegQ\[5\] 16.462 ns register " "Info: tco from clock \"CLK\" to destination pin \"DOUT\[6\]\" through register \"cntl_log:I_cntl_log\|ControlRegQ\[5\]\" is 16.462 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 1.673 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 1.673 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.890 ns) 0.890 ns CLK 1 CLK PIN_95 54 " "Info: 1: + IC(0.000 ns) + CELL(0.890 ns) = 0.890 ns; Loc. = PIN_95; Fanout = 54; CLK Node = 'CLK'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.783 ns) + CELL(0.000 ns) 1.673 ns cntl_log:I_cntl_log\|ControlRegQ\[5\] 2 REG LC8_4_A2 16 " "Info: 2: + IC(0.783 ns) + CELL(0.000 ns) = 1.673 ns; Loc. = LC8_4_A2; Fanout = 16; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[5\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.783 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[5] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.890 ns ( 53.20 % ) " "Info: Total cell delay = 0.890 ns ( 53.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.783 ns ( 46.80 % ) " "Info: Total interconnect delay = 0.783 ns ( 46.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { CLK {} CLK~out0 {} cntl_log:I_cntl_log|ControlRegQ[5] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.335 ns + " "Info: + Micro clock to output delay of source is 0.335 ns" { } { { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.454 ns + Longest register pin " "Info: + Longest register to pin delay is 14.454 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.161 ns) 0.161 ns cntl_log:I_cntl_log\|ControlRegQ\[5\] 1 REG LC8_4_A2 16 " "Info: 1: + IC(0.000 ns) + CELL(0.161 ns) = 0.161 ns; Loc. = LC8_4_A2; Fanout = 16; REG Node = 'cntl_log:I_cntl_log\|ControlRegQ\[5\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { cntl_log:I_cntl_log|ControlRegQ[5] } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 191 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.294 ns) + CELL(0.798 ns) 1.253 ns portcout:I_portcout\|PortCOutRegQ\[4\]~1555 2 COMB LC10_5_A2 6 " "Info: 2: + IC(0.294 ns) + CELL(0.798 ns) = 1.253 ns; Loc. = LC10_5_A2; Fanout = 6; COMB Node = 'portcout:I_portcout\|PortCOutRegQ\[4\]~1555'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.092 ns" { cntl_log:I_cntl_log|ControlRegQ[5] portcout:I_portcout|PortCOutRegQ[4]~1555 } "NODE_NAME" } } { "PORTCOUT.VHD" "" { Text "E:/Study/A8255/PORTCOUT.VHD" 356 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.083 ns) + CELL(0.890 ns) 3.226 ns cntl_log:I_cntl_log\|Mux0~72 3 COMB LC9_9_A2 16 " "Info: 3: + IC(1.083 ns) + CELL(0.890 ns) = 3.226 ns; Loc. = LC9_9_A2; Fanout = 16; COMB Node = 'cntl_log:I_cntl_log\|Mux0~72'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.973 ns" { portcout:I_portcout|PortCOutRegQ[4]~1555 cntl_log:I_cntl_log|Mux0~72 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 115 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.790 ns) + CELL(0.879 ns) 5.895 ns dout_mux:I_dout_mux\|Mux1~488 4 COMB LC9_1_E2 1 " "Info: 4: + IC(1.790 ns) + CELL(0.879 ns) = 5.895 ns; Loc. = LC9_1_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux1~488'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.669 ns" { cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux1~488 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.890 ns) 7.052 ns dout_mux:I_dout_mux\|Mux1~489 5 COMB LC5_1_E2 1 " "Info: 5: + IC(0.267 ns) + CELL(0.890 ns) = 7.052 ns; Loc. = LC5_1_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux1~489'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.157 ns" { dout_mux:I_dout_mux|Mux1~488 dout_mux:I_dout_mux|Mux1~489 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.743 ns) + CELL(0.890 ns) 9.685 ns dout_mux:I_dout_mux\|Mux1~490 6 COMB LC9_8_A2 1 " "Info: 6: + IC(1.743 ns) + CELL(0.890 ns) = 9.685 ns; Loc. = LC9_8_A2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux1~490'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.633 ns" { dout_mux:I_dout_mux|Mux1~489 dout_mux:I_dout_mux|Mux1~490 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.279 ns) + CELL(2.490 ns) 14.454 ns DOUT\[6\] 7 PIN PIN_112 0 " "Info: 7: + IC(2.279 ns) + CELL(2.490 ns) = 14.454 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'DOUT\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.769 ns" { dout_mux:I_dout_mux|Mux1~490 DOUT[6] } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.998 ns ( 48.42 % ) " "Info: Total cell delay = 6.998 ns ( 48.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.456 ns ( 51.58 % ) " "Info: Total interconnect delay = 7.456 ns ( 51.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.454 ns" { cntl_log:I_cntl_log|ControlRegQ[5] portcout:I_portcout|PortCOutRegQ[4]~1555 cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux1~488 dout_mux:I_dout_mux|Mux1~489 dout_mux:I_dout_mux|Mux1~490 DOUT[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.454 ns" { cntl_log:I_cntl_log|ControlRegQ[5] {} portcout:I_portcout|PortCOutRegQ[4]~1555 {} cntl_log:I_cntl_log|Mux0~72 {} dout_mux:I_dout_mux|Mux1~488 {} dout_mux:I_dout_mux|Mux1~489 {} dout_mux:I_dout_mux|Mux1~490 {} DOUT[6] {} } { 0.000ns 0.294ns 1.083ns 1.790ns 0.267ns 1.743ns 2.279ns } { 0.161ns 0.798ns 0.890ns 0.879ns 0.890ns 0.890ns 2.490ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.673 ns" { CLK cntl_log:I_cntl_log|ControlRegQ[5] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.673 ns" { CLK {} CLK~out0 {} cntl_log:I_cntl_log|ControlRegQ[5] {} } { 0.000ns 0.000ns 0.783ns } { 0.000ns 0.890ns 0.000ns } "" } } { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "14.454 ns" { cntl_log:I_cntl_log|ControlRegQ[5] portcout:I_portcout|PortCOutRegQ[4]~1555 cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux1~488 dout_mux:I_dout_mux|Mux1~489 dout_mux:I_dout_mux|Mux1~490 DOUT[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "14.454 ns" { cntl_log:I_cntl_log|ControlRegQ[5] {} portcout:I_portcout|PortCOutRegQ[4]~1555 {} cntl_log:I_cntl_log|Mux0~72 {} dout_mux:I_dout_mux|Mux1~488 {} dout_mux:I_dout_mux|Mux1~489 {} dout_mux:I_dout_mux|Mux1~490 {} DOUT[6] {} } { 0.000ns 0.294ns 1.083ns 1.790ns 0.267ns 1.743ns 2.279ns } { 0.161ns 0.798ns 0.890ns 0.879ns 0.890ns 0.890ns 2.490ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "A\[0\] DOUT\[6\] 17.351 ns Longest " "Info: Longest tpd from source pin \"A\[0\]\" to destination pin \"DOUT\[6\]\" is 17.351 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.240 ns) 1.240 ns A\[0\] 1 PIN PIN_25 40 " "Info: 1: + IC(0.000 ns) + CELL(1.240 ns) = 1.240 ns; Loc. = PIN_25; Fanout = 40; PIN Node = 'A\[0\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { A[0] } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 11 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.085 ns) + CELL(0.798 ns) 6.123 ns cntl_log:I_cntl_log\|Mux0~72 2 COMB LC9_9_A2 16 " "Info: 2: + IC(4.085 ns) + CELL(0.798 ns) = 6.123 ns; Loc. = LC9_9_A2; Fanout = 16; COMB Node = 'cntl_log:I_cntl_log\|Mux0~72'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.883 ns" { A[0] cntl_log:I_cntl_log|Mux0~72 } "NODE_NAME" } } { "CNTL_LOG.VHD" "" { Text "E:/Study/A8255/CNTL_LOG.VHD" 115 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.790 ns) + CELL(0.879 ns) 8.792 ns dout_mux:I_dout_mux\|Mux1~488 3 COMB LC9_1_E2 1 " "Info: 3: + IC(1.790 ns) + CELL(0.879 ns) = 8.792 ns; Loc. = LC9_1_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux1~488'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.669 ns" { cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux1~488 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.267 ns) + CELL(0.890 ns) 9.949 ns dout_mux:I_dout_mux\|Mux1~489 4 COMB LC5_1_E2 1 " "Info: 4: + IC(0.267 ns) + CELL(0.890 ns) = 9.949 ns; Loc. = LC5_1_E2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux1~489'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.157 ns" { dout_mux:I_dout_mux|Mux1~488 dout_mux:I_dout_mux|Mux1~489 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.743 ns) + CELL(0.890 ns) 12.582 ns dout_mux:I_dout_mux\|Mux1~490 5 COMB LC9_8_A2 1 " "Info: 5: + IC(1.743 ns) + CELL(0.890 ns) = 12.582 ns; Loc. = LC9_8_A2; Fanout = 1; COMB Node = 'dout_mux:I_dout_mux\|Mux1~490'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.633 ns" { dout_mux:I_dout_mux|Mux1~489 dout_mux:I_dout_mux|Mux1~490 } "NODE_NAME" } } { "DOUT_MUX.VHD" "" { Text "E:/Study/A8255/DOUT_MUX.VHD" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.279 ns) + CELL(2.490 ns) 17.351 ns DOUT\[6\] 6 PIN PIN_112 0 " "Info: 6: + IC(2.279 ns) + CELL(2.490 ns) = 17.351 ns; Loc. = PIN_112; Fanout = 0; PIN Node = 'DOUT\[6\]'" { } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.769 ns" { dout_mux:I_dout_mux|Mux1~490 DOUT[6] } "NODE_NAME" } } { "A8255.vhd" "" { Text "E:/Study/A8255/A8255.vhd" 17 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.187 ns ( 41.42 % ) " "Info: Total cell delay = 7.187 ns ( 41.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.164 ns ( 58.58 % ) " "Info: Total interconnect delay = 10.164 ns ( 58.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "17.351 ns" { A[0] cntl_log:I_cntl_log|Mux0~72 dout_mux:I_dout_mux|Mux1~488 dout_mux:I_dout_mux|Mux1~489 dout_mux:I_dout_mux|Mux1~490 DOUT[6] } "NODE_NAME" } } { "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/altera/72/quartus/bin/Technology_Viewer.qrui" "17.351 ns" { A[0] {} A[0]~out0 {} cntl_log:I_cntl_log|Mux0~72 {} dout_mux:I_dout_mux|Mux1~488 {} dout_mux:I_dout_mux|Mux1~489 {} dout_mux:I_dout_mux|Mux1~490 {} DOUT[6] {} } { 0.000ns 0.000ns 4.085ns 1.790ns 0.267ns 1.743ns 2.279ns } { 0.000ns 1.240ns 0.798ns 0.879ns 0.890ns 0.890ns 2.490ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
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