vhdlsiweichengfaqi.doc

这是一个利用MAX PULL 制作的VHDL的全加器的程序 如果有需要仿真图的 请叫站长联系我

------------------------------------------------------------------------/
-- DESCRIPTION   :  Signed mulitplier:
--                  A (A) input width : 4
--                  B (B) input width : 4
--                  Q (data_out) output width : 7
-- Download from :  http://www.pld.com.cn
--------------------------------------------------------------------------------/

library IEEE;
use IEEE.std_logic_1164.all;

entity one_bit_adder is
	port (
		A: in STD_LOGIC;
		B: in STD_LOGIC;
		C_in: in STD_LOGIC;
		S: out STD_LOGIC;
		C_out: out STD_LOGIC
	);
end one_bit_adder;

architecture one_bit_adder of one_bit_adder is
begin

	S <= A xor B xor C_in;
	C_out <= (A and B) or (C_in and (A xor B));

end one_bit_adder;


library IEEE;
use IEEE.std_logic_1164.all;

entity multi is
	port (
		A: in STD_LOGIC_VECTOR (3 downto 0);
		B: in STD_LOGIC_VECTOR (3 downto 0);
		data_out: out STD_LOGIC_VECTOR (6 downto 0)
	);
end multi;



architecture multi_arch of multi is
signal A_MULT_B0: STD_LOGIC_VECTOR (2 downto 0);
signal A_MULT_B1: STD_LOGIC_VECTOR (2 downto 0);
signal A_MULT_B2: STD_LOGIC_VECTOR (2 downto 0);

signal S_TEMP1: STD_LOGIC_VECTOR (1 downto 0);
signal S_TEMP2: STD_LOGIC_VECTOR (1 downto 0);

signal C_TEMP : STD_LOGIC_VECTOR (6 downto 0);

signal C0_out_B0, C1_out_B0, C2_out_B0 : STD_LOGIC;
signal C0_out_B1, C1_out_B1, C2_out_B1 : STD_LOGIC;

signal ZERO: STD_LOGIC;

component one_bit_adder
	port (
		A: in STD_LOGIC;
		B: in STD_LOGIC;
		C_in: in STD_LOGIC;
		S: out STD_LOGIC;
		C_out: out STD_LOGIC
		);
end component;
begin
	U_0_0 : one_bit_adder port map (A => A_MULT_B0(1), B => A_MULT_B1(0), C_in => ZERO, S => C_TEMP(1), C_out => C0_out_B0);
	U_0_1 : one_bit_adder port map (A => A_MULT_B0(2), B => A_MULT_B1(1), C_in => C0_out_B0, S => S_TEMP1(0), C_out => C1_out_B0);
	U_0_2 : one_bit_adder port map (A => ZERO, B => A_MULT_B1(2), C_in => C1_out_B0, S => S_TEMP1(1), C_out => C2_out_B0);

	U_1_0 : one_bit_adder port map (A => A_MULT_B2(0), B => S_TEMP1(0), C_in => ZERO, S => C_TEMP(2), C_out => C0_out_B1);
	U_1_1 : one_bit_adder port map (A => A_MULT_B2(1), B => S_TEMP1(1), C_in => C0_out_B1, S => S_TEMP2(0), C_out => C1_out_B1);
	U_1_2 : one_bit_adder port map (A => A_MULT_B2(2), B => C2_out_B0, C_in => C1_out_B1, S => S_TEMP2(1), C_out => C2_out_B1);

	A_MULT_B0(0) <= A (0) and B (0);
	A_MULT_B0(1) <= A (1) and B (0);
	A_MULT_B0(2) <= A (2) and B (0);

	A_MULT_B1(0) <= A (0) and B (1);
	A_MULT_B1(1) <= A (1) and B (1);
	A_MULT_B1(2) <= A (2) and B (1);

	A_MULT_B2(0) <= A (0) and B (2);
	A_MULT_B2(1) <= A (1) and B (2);
	A_MULT_B2(2) <= A (2) and B (2);

	ZERO <= '0';
	C_TEMP(0) <= A_MULT_B0(0);
	C_TEMP(4 downto 3) <=  S_TEMP2(1 downto 0);
	C_TEMP(5) <= C2_out_B1;

	C_TEMP(6) <= A(3) xor B(3);

	data_out <= C_TEMP;

end multi_arch;