adc.sim.qmsg

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· QMSG 代码 · 共 6 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 28 15:07:31 2007 " "Info: Processing started: Fri Dec 28 15:07:31 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off adc -c adc " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off adc -c adc" {  } {  } 0}
{ "Error" "ESIM_QSYN_NOT_RUN_FOR_SGATE" "adc " "Error: Run Generate Functional Simulation Netlist (quartus_map adc --generate_functional_sim_netlist) to generate functional simulation netlist for top level entity \"adc\" before running the Simulator (quartus_sim)" {  } {  } 0}
{ "Error" "EQEXE_ERROR_COUNT" "Simulator 1  0 s Quartus II " "Error: Quartus II Simulator was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Fri Dec 28 15:07:31 2007 " "Error: Processing ended: Fri Dec 28 15:07:31 2007" {  } {  } 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}