adc.qsf

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· QSF 代码 · 共 73 行

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic       
# functions, and any output files any of the foregoing           
# (including device programming or simulation files), and any    
# associated documentation or information are expressly subject  
# to the terms and conditions of the Altera Program License      
# Subscription Agreement, Altera MegaCore Function License       
# Agreement, or other applicable license agreement, including,   
# without limitation, that your use is for the sole purpose of   
# programming logic devices manufactured by Altera and sold by   
# Altera or its authorized distributors.  Please refer to the    
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		adc_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:58:48  DECEMBER 06, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "5.0 SP2"
set_global_assignment -name VERILOG_FILE ../did.v
set_global_assignment -name VERILOG_FILE ../adc_4/adc_4.v
set_global_assignment -name VERILOG_FILE ../adc_3/adc_3.v
set_global_assignment -name VERILOG_FILE ../adc_2/adc_2.v
set_global_assignment -name VERILOG_FILE ../adc_1/adc_1.v
set_global_assignment -name BDF_FILE ../adc_4/adc.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE adc.vwf

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_79 -to clk
set_location_assignment PIN_103 -to ad_sts
set_location_assignment PIN_104 -to control
set_location_assignment PIN_89 -to data_in[0]
set_location_assignment PIN_90 -to data_in[1]
set_location_assignment PIN_92 -to data_in[2]
set_location_assignment PIN_93 -to data_in[3]
set_location_assignment PIN_94 -to data_in[4]
set_location_assignment PIN_95 -to data_in[5]
set_location_assignment PIN_96 -to data_in[6]
set_location_assignment PIN_97 -to data_in[7]
set_location_assignment PIN_99 -to data_in[8]
set_location_assignment PIN_100 -to data_in[9]
set_location_assignment PIN_101 -to data_in[10]
set_location_assignment PIN_102 -to data_in[11]
set_location_assignment PIN_158 -to add_out1[0]
set_location_assignment PIN_159 -to add_out1[1]
set_location_assignment PIN_160 -to add_out1[2]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name FAMILY ACEX1K
set_global_assignment -name TOP_LEVEL_ENTITY adc

# Fitter Assignments
# ==================
set_global_assignment -name DEVICE "EP1K100QC208-1"
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1

# Simulator Assignments
# =====================
set_global_assignment -name SIMULATION_MODE FUNCTIONAL