adc_4.fit.eqn

用verilog编程实现的基于FPGA的AD数据采集程序

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L4Q is f_r~reg0 at LC2_C25
--operation mode is normal

A1L4Q_lut_out = reset & !A1L4Q;
A1L4Q = DFFEA(A1L4Q_lut_out, !GLOBAL(ad_sts), , , , , );

--A1L3Q is f_r~10 at LC2_C25
--operation mode is normal

A1L3Q = A1L4Q;


--reset is reset at PIN_184
--operation mode is input

reset = INPUT();


--ad_sts is ad_sts at PIN_79
--operation mode is input

ad_sts = INPUT();


--f_r is f_r at PIN_140
--operation mode is output

f_r = OUTPUT(A1L4Q);