adc_4.map.summary

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Thu Dec 06 19:47:37 2007
Quartus II Version : 5.0 Build 171 11/03/2005 SP 2 SJ Full Version
Revision Name : adc_4
Top-level Entity Name : adc_4
Family : ACEX1K
Device : EP1K100QC208-1
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 1
Total pins : 3
Total memory bits : 0
Total PLLs : 0