adc_4.tan.summary

用verilog编程实现的基于FPGA的AD数据采集程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 1.500 ns
From           : reset
To             : f_r~reg0
From Clock     : 
To Clock       : ad_sts
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.300 ns
From           : f_r~reg0
To             : f_r
From Clock     : ad_sts
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.600 ns
From           : reset
To             : f_r~reg0
From Clock     : 
To Clock       : ad_sts
Failed Paths   : 0

Type           : Clock Setup: 'ad_sts'
Slack          : N/A
Required Time  : None
Actual Time    : Restricted to 333.33 MHz ( period = 3.000 ns )
From           : f_r~reg0
To             : f_r~reg0
From Clock     : ad_sts
To Clock       : ad_sts
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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