adc_2.map.summary

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· SUMMARY 代码 · 共 13 行

Flow Status : Successful - Fri Dec 28 14:11:09 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : adc_2
Top-level Entity Name : adc_2
Family : ACEX1K
Device : EP1K100QC208-1
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 8
Total pins : 11
Total memory bits : 0
Total PLLs : 0