adc_2.tan.qmsg

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· QMSG 代码 · 共 8 行

QMSG
8
字号
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 28 14:11:24 2007 " "Info: Processing started: Fri Dec 28 14:11:24 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off adc_2 -c adc_2 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off adc_2 -c adc_2" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "add\[2\] sel8 8.100 ns Longest " "Info: Longest tpd from source pin \"add\[2\]\" to destination pin \"sel8\" is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 0.300 ns add\[2\] 1 PIN PIN_184 8 " "Info: 1: + IC(0.000 ns) + CELL(0.300 ns) = 0.300 ns; Loc. = PIN_184; Fanout = 8; PIN Node = 'add\[2\]'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2_cmp.qrpt" Compiler "adc_2" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/" "" "" { add[2] } "NODE_NAME" } "" } } { "adc_2.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/adc_2.v" 2 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(0.700 ns) 2.700 ns Decoder~77 2 COMB LC2_J22 1 " "Info: 2: + IC(1.700 ns) + CELL(0.700 ns) = 2.700 ns; Loc. = LC2_J22; Fanout = 1; COMB Node = 'Decoder~77'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2_cmp.qrpt" Compiler "adc_2" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/" "" "2.400 ns" { add[2] Decoder~77 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.400 ns) 8.100 ns sel8 3 PIN PIN_175 0 " "Info: 3: + IC(1.000 ns) + CELL(4.400 ns) = 8.100 ns; Loc. = PIN_175; Fanout = 0; PIN Node = 'sel8'" {  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2_cmp.qrpt" Compiler "adc_2" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/" "" "5.400 ns" { Decoder~77 sel8 } "NODE_NAME" } "" } } { "adc_2.v" "" { Text "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/adc_2.v" 3 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.400 ns 66.67 % " "Info: Total cell delay = 5.400 ns ( 66.67 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns 33.33 % " "Info: Total interconnect delay = 2.700 ns ( 33.33 % )" {  } {  } 0}  } { { "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2_cmp.qrpt" "" { Report "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2_cmp.qrpt" Compiler "adc_2" "UNKNOWN" "V1" "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/db/adc_2.quartus_db" { Floorplan "D:/altera/qdesigns50/zdx/ADC模块_r/adc_2/" "" "8.100 ns" { add[2] Decoder~77 sel8 } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "8.100 ns" { add[2] add[2]~out Decoder~77 sel8 } { 0.000ns 0.000ns 1.700ns 1.000ns } { 0.000ns 0.300ns 0.700ns 4.400ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Dec 28 14:11:24 2007 " "Info: Processing ended: Fri Dec 28 14:11:24 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}

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