adc_2.sim.qmsg

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· QMSG 代码 · 共 10 行

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 06 18:26:41 2007 " "Info: Processing started: Thu Dec 06 18:26:41 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off adc_2 -c adc_2 " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off adc_2 -c adc_2" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|adc_2\|add\[2\] " "Warning: Can't find signal in vector source file for input pin \"\|adc_2\|add\[2\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|adc_2\|add\[0\] " "Warning: Can't find signal in vector source file for input pin \"\|adc_2\|add\[0\]\"" {  } {  } 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|adc_2\|add\[1\] " "Warning: Can't find signal in vector source file for input pin \"\|adc_2\|add\[1\]\"" {  } {  } 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "      0.00 % " "Info: Simulation coverage is       0.00 %" {  } {  } 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "0 " "Info: Number of transitions in simulation is 0" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 3 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 06 18:26:42 2007 " "Info: Processing ended: Thu Dec 06 18:26:42 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0}