adc_2.map.eqn

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· EQN 代码 · 共 168 行

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L1 is Decoder~70
--operation mode is normal

A1L1 = add[2] & add[0] & add[1];

--A1L9 is Decoder~78
--operation mode is normal

A1L9 = add[2] & add[0] & add[1];


--A1L2 is Decoder~71
--operation mode is normal

A1L2 = add[2] & add[1] & (!add[0]);

--A1L01 is Decoder~79
--operation mode is normal

A1L01 = add[2] & add[1] & (!add[0]);


--A1L3 is Decoder~72
--operation mode is normal

A1L3 = add[2] & add[0] & (!add[1]);

--A1L11 is Decoder~80
--operation mode is normal

A1L11 = add[2] & add[0] & (!add[1]);


--A1L4 is Decoder~73
--operation mode is normal

A1L4 = add[2] & (!add[0] & !add[1]);

--A1L21 is Decoder~81
--operation mode is normal

A1L21 = add[2] & (!add[0] & !add[1]);


--A1L5 is Decoder~74
--operation mode is normal

A1L5 = add[0] & add[1] & (!add[2]);

--A1L31 is Decoder~82
--operation mode is normal

A1L31 = add[0] & add[1] & (!add[2]);


--A1L6 is Decoder~75
--operation mode is normal

A1L6 = add[1] & (!add[2] & !add[0]);

--A1L41 is Decoder~83
--operation mode is normal

A1L41 = add[1] & (!add[2] & !add[0]);


--A1L7 is Decoder~76
--operation mode is normal

A1L7 = add[0] & (!add[2] & !add[1]);

--A1L51 is Decoder~84
--operation mode is normal

A1L51 = add[0] & (!add[2] & !add[1]);


--A1L8 is Decoder~77
--operation mode is normal

A1L8 = !add[2] & !add[0] & !add[1];

--A1L61 is Decoder~85
--operation mode is normal

A1L61 = !add[2] & !add[0] & !add[1];


--add[2] is add[2]
--operation mode is input

add[2] = INPUT();


--add[0] is add[0]
--operation mode is input

add[0] = INPUT();


--add[1] is add[1]
--operation mode is input

add[1] = INPUT();


--sel1 is sel1
--operation mode is output

sel1 = OUTPUT(A1L1);


--sel2 is sel2
--operation mode is output

sel2 = OUTPUT(A1L2);


--sel3 is sel3
--operation mode is output

sel3 = OUTPUT(A1L3);


--sel4 is sel4
--operation mode is output

sel4 = OUTPUT(A1L4);


--sel5 is sel5
--operation mode is output

sel5 = OUTPUT(A1L5);


--sel6 is sel6
--operation mode is output

sel6 = OUTPUT(A1L6);


--sel7 is sel7
--operation mode is output

sel7 = OUTPUT(A1L7);


--sel8 is sel8
--operation mode is output

sel8 = OUTPUT(A1L8);