adc_1.v

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· Verilog 代码 · 共 60 行

module adc_1(clk,f_r,add,add_out,control);
input clk,f_r;//clk周期为120ns
output[2:0] add;
output control;
output [2:0]add_out;
reg beg;
reg flag;//读完成标志位
//reg[2:0] add;
reg control;
assign add=3'b111;
always@(posedge clk)
begin
    if(beg==1'b0)//第一次转换触发
      begin
       control<=1'b0;// R/C置低
       beg<=1'b1;
       flag<=1'b0;
      end
    else
      begin
       if(flag==f_r)
        begin
         control<=1'b1;
         beg<=1'b1;//未转换完成，等待
        end
       else
        begin
         control<=1'b0;// R/C置低
         beg<=1'b1;
         flag<=f_r;
        end
         
      end
end
endmodule  

/*always@(posedge clk)
begin
 if(num==5'b00000)
   begin  
   control<=1'b0;
   num<=num+5'b00001;
  end
 else if(num==5'b10100)
  begin
  num<=5'b00000;
  control<=1'b1;
 end
else
 begin
  num<=num+5'b00001;
  control<=1'b1;
 end
end*/