adc_3.map.rpt

用verilog编程实现的基于FPGA的AD数据采集程序

; I/O pins                        ; 26        ;
; Total memory bits               ; 96        ;
; Maximum fan-out node            ; num[0]    ;
; Maximum fan-out                 ; 18        ;
; Total fan-out                   ; 138       ;
; Average fan-out                 ; 3.14      ;
+---------------------------------+-----------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                               ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+----------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name        ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+----------------------------+
; |adc_3                     ; 6 (5)       ; 3            ; 96          ; 26   ; 3 (2)        ; 1 (1)             ; 2 (2)            ; 0 (0)           ; |adc_3                     ;
;    |altdpram:mema_rtl_0|   ; 1 (1)       ; 0            ; 96          ; 0    ; 1 (1)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; |adc_3|altdpram:mema_rtl_0 ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+----------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                  ;
+-----------------------------+-----------+--------------+--------------+--------------+--------------+------+------+
; Name                        ; Mode      ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+-----------------------------+-----------+--------------+--------------+--------------+--------------+------+------+
; altdpram:mema_rtl_0|content ; Dual Port ; 8            ; 12           ; 8            ; 12           ; 96   ; none ;
+-----------------------------+-----------+--------------+--------------+--------------+--------------+------+------+


+----------------------------------------------------------------------------------------+
; Registers Protected by SYN_PRESERVE, DONT_TOUCH                                        ;
+---------------+---------------------------+--------------------------------------------+
; Register Name ; Protected by SYN_PRESERVE ; Not to be Touched by Netlist Optimizations ;
+---------------+---------------------------+--------------------------------------------+
; num[0]        ; yes                       ; yes                                        ;
; num[1]        ; yes                       ; yes                                        ;
; num[2]        ; yes                       ; yes                                        ;
+---------------+---------------------------+--------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 3     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 3     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+----------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: altdpram:mema_rtl_0 ;
+-------------------------------------+--------------+-----------------+
; Parameter Name                      ; Value        ; Type            ;
+-------------------------------------+--------------+-----------------+
; WIDTH                               ; 12           ; Untyped         ;
; WIDTHAD                             ; 3            ; Untyped         ;
; NUMWORDS                            ; 8            ; Untyped         ;
; FILE                                ; UNUSED       ; Untyped         ;
; LPM_FILE                            ; UNUSED       ; Untyped         ;
; INDATA_REG                          ; INCLOCK      ; Untyped         ;
; INDATA_ACLR                         ; OFF          ; Untyped         ;
; WRADDRESS_REG                       ; INCLOCK      ; Untyped         ;
; WRADDRESS_ACLR                      ; OFF          ; Untyped         ;
; WRCONTROL_REG                       ; INCLOCK      ; Untyped         ;
; WRCONTROL_ACLR                      ; OFF          ; Untyped         ;
; RDADDRESS_REG                       ; OUTCLOCK     ; Untyped         ;
; RDADDRESS_ACLR                      ; OFF          ; Untyped         ;
; RDCONTROL_REG                       ; UNREGISTERED ; Untyped         ;
; RDCONTROL_ACLR                      ; OFF          ; Untyped         ;
; OUTDATA_REG                         ; OUTCLOCK     ; Untyped         ;
; OUTDATA_ACLR                        ; OFF          ; Untyped         ;
; USE_EAB                             ; ON           ; Untyped         ;
; MAXIMUM_DEPTH                       ; 2048         ; Untyped         ;
; DEVICE_FAMILY                       ; ACEX1K       ; Untyped         ;
; SUPPRESS_MEMORY_CONVERSION_WARNINGS ; OFF          ; Untyped         ;
; INTENDED_DEVICE_FAMILY              ; APEX20KE     ; Untyped         ;
; ENABLE_RAM_BENCHMARKING_MODE        ; OFF          ; Untyped         ;
; AUTO_CARRY_CHAINS                   ; ON           ; AUTO_CARRY      ;
; IGNORE_CARRY_BUFFERS                ; OFF          ; IGNORE_CARRY    ;
; AUTO_CASCADE_CHAINS                 ; ON           ; AUTO_CASCADE    ;
; IGNORE_CASCADE_BUFFERS              ; OFF          ; IGNORE_CASCADE  ;
+-------------------------------------+--------------+-----------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/adc_3/adc_3.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Dec 06 16:48:38 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off adc_3 -c adc_3
Info: Found 1 design units, including 1 entities, in source file adc_3.v
    Info: Found entity 1: adc_3
Info: Elaborating entity "adc_3" for the top level hierarchy
Info: Inferred 1 megafunctions from design logic
    Info: Inferred altdpram megafunction (NUMWORDS=8, WIDTH=12) from the following logic: "mema~0"
Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus50/libraries/megafunctions/altdpram.tdf
    Info: Found entity 1: altdpram
Info: Issued messages during elaboration of megafunction "altdpram:mema_rtl_0"
Warning: Memory Initialization File or Hexadecimal (Intel-Format) File for RAM is not specified -- setting initial contents to 0
    Warning: RAM name is "segment[0][11]"
    Warning: RAM name is "segment[0][10]"
    Warning: RAM name is "segment[0][9]"
    Warning: RAM name is "segment[0][8]"
    Warning: RAM name is "segment[0][7]"
    Warning: RAM name is "segment[0][6]"
    Warning: RAM name is "segment[0][5]"
    Warning: RAM name is "segment[0][4]"
    Warning: RAM name is "segment[0][3]"
    Warning: RAM name is "segment[0][2]"
    Warning: RAM name is "segment[0][1]"
    Warning: RAM name is "segment[0][0]"
Info: Implemented 44 device resources after synthesis - the final resource count might be different
    Info: Implemented 14 input pins
    Info: Implemented 12 output pins
    Info: Implemented 6 logic cells
    Info: Implemented 12 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
    Info: Processing ended: Thu Dec 06 16:48:39 2007
    Info: Elapsed time: 00:00:01