adc_3.v

来自「用verilog编程实现的基于FPGA的AD数据采集程序」· Verilog 代码 · 共 31 行

module adc_3(sel,ad_sts,data_in,data_out);
input sel;
input ad_sts;
input[11:0] data_in;
output[11:0] data_out;
reg[11:0] mema[7:0];
reg[11:0] data_out;
reg[2:0] num;
always@(negedge ad_sts)
 begin
  if(sel)
    begin 
     if(num==3'b111)
      begin
       num<=3'b000;
       mema[num]<=data_in;
       data_out<=data_in;
      end
     else
      begin
       num<=num+3'b001;
       mema[num]<=data_in;
       data_out<=data_in;
      end
    end
  else
    num<=num;
 end
endmodule