adc_3.tan.summary

用verilog编程实现的基于FPGA的AD数据采集程序

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.400 ns
From           : data_in[9]
To             : altdpram:mema_rtl_0|q[9]~reg_in
From Clock     : 
To Clock       : ad_sts
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.000 ns
From           : altdpram:mema_rtl_0|q[8]
To             : data_out[8]
From Clock     : ad_sts
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.300 ns
From           : sel
To             : num[2]
From Clock     : 
To Clock       : ad_sts
Failed Paths   : 0

Type           : Clock Setup: 'ad_sts'
Slack          : N/A
Required Time  : None
Actual Time    : 196.08 MHz ( period = 5.100 ns )
From           : altdpram:mema_rtl_0|q[0]~reg_wa2
To             : altdpram:mema_rtl_0|q[0]
From Clock     : ad_sts
To Clock       : ad_sts
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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