secondwatch.tan.rpt

用VERILOG实现的秒表 用VERILOG实现的秒表

; Worst-case th                ; N/A                                      ; None          ; 5.636 ns                         ; reset_n                                                                                 ; fpcount:fpcount_sl|cp                                                                   ; --         ; clkin    ; 0            ;
; Clock Setup: 'clkin'         ; N/A                                      ; None          ; 128.27 MHz ( period = 7.796 ns ) ; fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|safe_q[15] ; fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|safe_q[15] ; clkin      ; clkin    ; 0            ;
; Clock Hold: 'clkin'          ; Not operational: Clock Skew > Data Delay ; None          ; N/A                              ; jscount:jscount_sl|count[3]                                                             ; jscount:jscount_sl|count[3]                                                             ; clkin      ; clkin    ; 53           ;
; Total number of failed paths ;                                          ;               ;                                  ;                                                                                         ;                                                                                         ;            ;          ; 53           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clkin           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clkin'                                                                                                                                                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                    ; To                                                                                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 128.27 MHz ( period = 7.796 ns )                    ; fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|safe_q[15] ; fenpin:fenpin_inst|lpm_counter:lpm_counter_component|cntr_mdj:auto_generated|safe_q[6]  ; clkin      ; clkin    ; None                        ; None                      ; 7.535 ns                ;