xkcon.tan.summary

用VHDL语言写的程序包含如下功能：1.键盘扫描2.控制AD转换3.产生PWM信号与51系列CPU接口

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.000 ns
From           : databus[7]
To             : pwm_count[7]
From Clock     : 
To Clock       : wr
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 61.000 ns
From           : port_no[1]
To             : databus[7]
From Clock     : ale
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 39.000 ns
From           : rd
To             : databus[7]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 6.000 ns
From           : adflag
To             : count_ad[7]
From Clock     : 
To Clock       : clk8mhz
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 12.000 ns
From           : clk200khz
To             : t200khz
From Clock     : clk8mhz
To Clock       : 
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 32.000 ns
From           : lcdcs1
To             : lcdcs2
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk8mhz'
Slack          : 56.000 ns
Required Time  : 8.00 MHz ( period = 125.000 ns )
Actual Time    : 14.49 MHz ( period = 69.000 ns )
From           : lpm_counter:count_rtl_1|dffs[5]
To             : pwm_pina~reg0
From Clock     : clk8mhz
To Clock       : clk8mhz
Failed Paths   : 0

Type           : Clock Setup: 'wr'
Slack          : 99.000 ns
Required Time  : 8.00 MHz ( period = 125.000 ns )
Actual Time    : 38.46 MHz ( period = 26.000 ns )
From           : begin_ad
To             : begin_ad
From Clock     : wr
To Clock       : wr
Failed Paths   : 0

Type           : Clock Hold: 'clk8mhz'
Slack          : 5.000 ns
Required Time  : 8.00 MHz ( period = 125.000 ns )
Actual Time    : N/A
From           : count_ad[0]
To             : count_ad[0]
From Clock     : clk8mhz
To Clock       : clk8mhz
Failed Paths   : 0

Type           : Clock Hold: 'wr'
Slack          : 18.000 ns
Required Time  : 8.00 MHz ( period = 125.000 ns )
Actual Time    : N/A
From           : begin_ad
To             : begin_ad
From Clock     : wr
To Clock       : wr
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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