xkcon.tan.rpt

用VHDL语言写的程序包含如下功能：1.键盘扫描2.控制AD转换3.产生PWM信号与51系列CPU接口

+------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------+---------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EPM7128SLC84-15    ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; fmax Requirement                                      ; 8.0 MHz            ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk8mhz         ;                    ; User Pin ; 8.0 MHz          ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; wr              ;                    ; User Pin ; 8.0 MHz          ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
; ale             ;                    ; User Pin ; 8.0 MHz          ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk8mhz'                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                               ; To                                 ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------+------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 56.000 ns                               ; 14.49 MHz ( period = 69.000 ns )                    ; lpm_counter:count_rtl_1|dffs[5]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 64.000 ns               ;
; 56.000 ns                               ; 14.49 MHz ( period = 69.000 ns )                    ; lpm_counter:count_rtl_1|dffs[4]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 64.000 ns               ;
; 56.000 ns                               ; 14.49 MHz ( period = 69.000 ns )                    ; lpm_counter:count_rtl_1|dffs[3]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 64.000 ns               ;
; 56.000 ns                               ; 14.49 MHz ( period = 69.000 ns )                    ; lpm_counter:count_rtl_1|dffs[2]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 64.000 ns               ;
; 56.000 ns                               ; 14.49 MHz ( period = 69.000 ns )                    ; lpm_counter:count_rtl_1|dffs[1]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 64.000 ns               ;
; 58.500 ns                               ; Restricted to 83.33 MHz ( period = 12.0 ns )        ; clk200khz                          ; lpm_counter:scan_cnt_rtl_0|dffs[1] ; clk8mhz    ; clk8mhz  ; 62.500 ns                   ; 79.500 ns                 ; 21.000 ns               ;
; 58.500 ns                               ; Restricted to 83.33 MHz ( period = 12.0 ns )        ; clk200khz                          ; lpm_counter:scan_cnt_rtl_0|dffs[0] ; clk8mhz    ; clk8mhz  ; 62.500 ns                   ; 79.500 ns                 ; 21.000 ns               ;
; 58.500 ns                               ; Restricted to 83.33 MHz ( period = 12.0 ns )        ; clk200khz                          ; lpm_counter:scan_cnt_rtl_0|dffs[2] ; clk8mhz    ; clk8mhz  ; 62.500 ns                   ; 79.500 ns                 ; 21.000 ns               ;
; 58.500 ns                               ; Restricted to 83.33 MHz ( period = 12.0 ns )        ; clk200khz                          ; lpm_counter:scan_cnt_rtl_0|dffs[3] ; clk8mhz    ; clk8mhz  ; 62.500 ns                   ; 79.500 ns                 ; 21.000 ns               ;
; 77.000 ns                               ; 20.83 MHz ( period = 48.000 ns )                    ; lpm_counter:count_rtl_1|dffs[11]   ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 43.000 ns               ;
; 77.000 ns                               ; 20.83 MHz ( period = 48.000 ns )                    ; lpm_counter:count_rtl_1|dffs[10]   ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 43.000 ns               ;
; 77.000 ns                               ; 20.83 MHz ( period = 48.000 ns )                    ; lpm_counter:count_rtl_1|dffs[9]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 43.000 ns               ;
; 77.000 ns                               ; 20.83 MHz ( period = 48.000 ns )                    ; lpm_counter:count_rtl_1|dffs[0]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 43.000 ns               ;
; 78.000 ns                               ; 21.28 MHz ( period = 47.000 ns )                    ; lpm_counter:count_rtl_1|dffs[8]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 42.000 ns               ;
; 78.000 ns                               ; 21.28 MHz ( period = 47.000 ns )                    ; lpm_counter:count_rtl_1|dffs[7]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 42.000 ns               ;
; 78.000 ns                               ; 21.28 MHz ( period = 47.000 ns )                    ; lpm_counter:count_rtl_1|dffs[6]    ; pwm_pina~reg0                      ; clk8mhz    ; clk8mhz  ; 125.000 ns                  ; 120.000 ns                ; 42.000 ns               ;