xkcon.tan.rpt

用VHDL语言写的程序包含如下功能：1.键盘扫描2.控制AD转换3.产生PWM信号与51系列CPU接口

Timing Analyzer report for xkcon
Fri Dec 30 09:48:37 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk8mhz'
  6. Clock Setup: 'wr'
  7. Clock Hold: 'clk8mhz'
  8. Clock Hold: 'wr'
  9. tsu
 10. tco
 11. tpd
 12. th
 13. Minimum tco
 14. Minimum tpd
 15. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                 ;
+------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------+---------------+------------+----------+--------------+
; Type                         ; Slack     ; Required Time                    ; Actual Time                      ; From                            ; To            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------+---------------+------------+----------+--------------+
; Worst-case tsu               ; N/A       ; None                             ; 4.000 ns                         ; databus[7]                      ; pwm_count[7]  ;            ; wr       ; 0            ;
; Worst-case tco               ; N/A       ; None                             ; 61.000 ns                        ; port_no[1]                      ; databus[7]    ; ale        ;          ; 0            ;
; Worst-case tpd               ; N/A       ; None                             ; 39.000 ns                        ; rd                              ; databus[7]    ;            ;          ; 0            ;
; Worst-case th                ; N/A       ; None                             ; 6.000 ns                         ; adflag                          ; count_ad[7]   ;            ; clk8mhz  ; 0            ;
; Worst-case Minimum tco       ; N/A       ; None                             ; 12.000 ns                        ; clk200khz                       ; t200khz       ; clk8mhz    ;          ; 0            ;
; Worst-case Minimum tpd       ; N/A       ; None                             ; 32.000 ns                        ; lcdcs1                          ; lcdcs2        ;            ;          ; 0            ;
; Clock Setup: 'clk8mhz'       ; 56.000 ns ; 8.00 MHz ( period = 125.000 ns ) ; 14.49 MHz ( period = 69.000 ns ) ; lpm_counter:count_rtl_1|dffs[5] ; pwm_pina~reg0 ; clk8mhz    ; clk8mhz  ; 0            ;
; Clock Setup: 'wr'            ; 99.000 ns ; 8.00 MHz ( period = 125.000 ns ) ; 38.46 MHz ( period = 26.000 ns ) ; begin_ad                        ; begin_ad      ; wr         ; wr       ; 0            ;
; Clock Hold: 'clk8mhz'        ; 5.000 ns  ; 8.00 MHz ( period = 125.000 ns ) ; N/A                              ; count_ad[0]                     ; count_ad[0]   ; clk8mhz    ; clk8mhz  ; 0            ;
; Clock Hold: 'wr'             ; 18.000 ns ; 8.00 MHz ( period = 125.000 ns ) ; N/A                              ; begin_ad                        ; begin_ad      ; wr         ; wr       ; 0            ;
; Total number of failed paths ;           ;                                  ;                                  ;                                 ;               ;            ;          ; 0            ;