xkcon.drc.rpt

用VHDL语言写的程序包含如下功能：1.键盘扫描2.控制AD转换3.产生PWM信号与51系列CPU接口

Design Assistant report for xkcon
Sat Nov 12 16:53:53 2005
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Design Assistant Summary
  3. Design Assistant Settings
  4. High Violations
  5. Medium Violations
  6. Information only Violations
  7. Design Assistant Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
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and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
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Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+---------------------------------------------------------------------------+
; Design Assistant Summary                                                  ;
+-----------------------------------+---------------------------------------+
; Design Assistant Status           ; Successful - Sat Nov 12 16:53:53 2005 ;
; Revision Name                     ; xkcon                                 ;
; Top-level Entity Name             ; xkcon                                 ;
; Family                            ; MAX7000S                              ;
; Total Critical Violations         ; 0                                     ;
; Total High Violations             ; 4                                     ;
; Total Medium Violations           ; 4                                     ;
; Total Information only Violations ; 56                                    ;
+-----------------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings                                                                                                                                                                                                                                                                     ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Option                                                                                                                                                                                                                                                                         ; Setting      ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Design Assistant mode                                                                                                                                                                                                                                                          ; Post-Fitting ;
; Minimum number of node fan-out                                                                                                                                                                                                                                                 ; 30           ;
; Maximum number of nodes to report                                                                                                                                                                                                                                              ; 50           ;
; Gated clock should be implemented according to Altera standard scheme                                                                                                                                                                                                          ; On           ;
; Logic cell should not be used to generate inverted clock                                                                                                                                                                                                                       ; On           ;
; Input clock pin should fan out to only one set of clock gating logic                                                                                                                                                                                                           ; On           ;
; Clock signal source should drive only input clock ports                                                                                                                                                                                                                        ; On           ;
; Clock signal should be a global signal (This rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On           ;
; Clock signal source should not drive registers that are triggered by different clock edges                                                                                                                                                                                     ; On           ;
; Combinational logic used as reset signal should be synchronized                                                                                                                                                                                                                ; On           ;
; External reset should be synchronized using two cascaded registers                                                                                                                                                                                                             ; On           ;
; External reset should be correctly synchronized                                                                                                                                                                                                                                ; On           ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be synchronized                                                                                                                                                        ; On           ;
; Reset signal that is generated in one clock domain and used in other, asynchronous clock domains should be correctly synchronized                                                                                                                                              ; On           ;
; Nodes with more than specified number of fan-outs                                                                                                                                                                                                                              ; On           ;
; Top nodes with highest fan-out                                                                                                                                                                                                                                                 ; On           ;
; Register output directly drives input of another register when both registers are triggered at same time                                                                                                                                                                       ; On           ;
; Registers in direct data transfer between clock domains are triggered by clock edges at the same time                                                                                                                                                                          ; On           ;
; Design should not contain combinational loops                                                                                                                                                                                                                                  ; On           ;
; Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                                ; On           ;
; Design should not contain delay chains                                                                                                                                                                                                                                         ; On           ;
; Design should not contain ripple clock structures                                                                                                                                                                                                                              ; On           ;
; Pulses should not be implemented asynchronously                                                                                                                                                                                                                                ; On           ;
; Multiple pulses should not be generated in design                                                                                                                                                                                                                              ; On           ;
; Design should not contain SR latches                                                                                                                                                                                                                                           ; On           ;
; Design should not contain latches                                                                                                                                                                                                                                              ; On           ;
; Combinational logic should not directly drive write enable signal of asynchronous RAM                                                                                                                                                                                          ; On           ;
; Design should not contain asynchronous memory                                                                                                                                                                                                                                  ; On           ;
; Output enable and input of same tri-state node should not be driven by same signal source                                                                                                                                                                                      ; On           ;
; Synchronous port and reset port of same register should not be driven by same signal source                                                                                                                                                                                    ; On           ;
; Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                             ; On           ;
; Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in receiving clock domain                                                                                                                          ; On           ;
; Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                                   ; On           ;
; Only one VREF pin should be assigned to HardCopy test pin in an I/O bank (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On           ;
; PLL drives multiple clock network types (This rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.)                                  ; On           ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+


+----------------------------------------------------+
; High Violations                                    ;
+----------------------------------------+-----------+
; Rule name                              ; Name      ;
+----------------------------------------+-----------+
; Clock signal should be a global signal ; clk200khz ;
; Clock signal should be a global signal ; clk2mhz   ;
; Clock signal should be a global signal ; wr        ;
; Clock signal should be a global signal ; ale       ;
+----------------------------------------+-----------+


+--------------------------------------------------------------------------------------------------------+
; Medium Violations                                                                                      ;
+--------------------------------------------------------------------------------------------+-----------+
; Rule name                                                                                  ; Name      ;
+--------------------------------------------------------------------------------------------+-----------+
; Clock signal source should drive only input clock ports                                    ; clk200khz ;
; Clock signal source should drive only input clock ports                                    ; clk2mhz   ;
; Clock signal source should not drive registers that are triggered by different clock edges ; clk2mhz   ;
; External reset should be synchronized using two cascaded registers                         ; reset     ;
+--------------------------------------------------------------------------------------------+-----------+


+--------------------------------------------------------------------------------------------------+
; Information only Violations                                                                      ;
+---------------------------------------------------+------------------------------------+---------+
; Rule name                                         ; Name                               ; Fan-Out ;
+---------------------------------------------------+------------------------------------+---------+
; Nodes with more than specified number of fan-outs ; c_st~7                             ; 31      ;