📄 xkcon.fit.rpt
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; Output enables ; 1 / 6 ( 16 % ) ;
; PIA buffers ; 229 / 288 ( 79 % ) ;
; PIAs ; 260 / 288 ( 90 % ) ;
+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 32.50) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 0 ;
; 12 - 14 ; 0 ;
; 15 - 17 ; 0 ;
; 18 - 20 ; 0 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 1 ;
; 27 - 29 ; 0 ;
; 30 - 32 ; 1 ;
; 33 - 35 ; 6 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 14.00) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 1 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 1 ;
; 15 ; 3 ;
; 16 ; 2 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 16 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 3.50) ; Number of LABs (Total = 6) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 2 ;
; 1 ; 0 ;
; 2 ; 4 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 1 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 1 ;
+-------------------------------------------------+-----------------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC3 ; databus[0], outpa[0]~reg0, wr, cs, port_no[0], port_no[2], port_no[1], cpu_write~50 ; outpa[0]~reg0, outpa[0] ;
; A ; LC9 ; lpm_counter:count_rtl_1|dffs[1], lpm_counter:count_rtl_1|dffs[0], reset, clk2mhz ; lpm_counter:count_rtl_1|dffs[3], lpm_counter:count_rtl_1|dffs[4], lpm_counter:count_rtl_1|dffs[5], lpm_counter:count_rtl_1|dffs[6], lpm_counter:count_rtl_1|dffs[7], lpm_counter:count_rtl_1|dffs[8], lpm_counter:count_rtl_1|dffs[9], lpm_counter:count_rtl_1|dffs[10], lpm_counter:count_rtl_1|dffs[11], LessThan~659, LessThan~666 ;
; A ; LC1 ; lpm_counter:count_rtl_1|dffs[2], lpm_counter:count_rtl_1|dffs[1], lpm_counter:count_rtl_1|dffs[0], reset, clk2mhz ; lpm_counter:count_rtl_1|dffs[4], lpm_counter:count_rtl_1|dffs[5], lpm_counter:count_rtl_1|dffs[6], lpm_counter:count_rtl_1|dffs[7], lpm_counter:count_rtl_1|dffs[8], lpm_counter:count_rtl_1|dffs[9], lpm_counter:count_rtl_1|dffs[10], lpm_counter:count_rtl_1|dffs[11], LessThan~658, LessThan~666 ;
; A ; LC10 ; lpm_counter:count_rtl_1|dffs[3], lpm_counter:count_rtl_1|dffs[2], lpm_counter:count_rtl_1|dffs[1], lpm_counter:count_rtl_1|dffs[0], reset, clk2mhz ; lpm_counter:count_rtl_1|dffs[5], lpm_counter:count_rtl_1|dffs[6], lpm_counter:count_rtl_1|dffs[7], lpm_counter:count_rtl_1|dffs[8], lpm_counter:count_rtl_1|dffs[9], lpm_counter:count_rtl_1|dffs[10], lpm_counter:count_rtl_1|dffs[11], LessThan~657, LessThan~666 ;
; A ; LC13 ; lpm_counter:scan_cnt_rtl_0|dffs[3], lpm_counter:scan_cnt_rtl_0|dffs[2] ; keyout[0] ;
; A ; LC8 ; lpm_counter:scan_cnt_rtl_0|dffs[3], lpm_counter:scan_cnt_rtl_0|dffs[2] ; keyout[2] ;
; A ; LC11 ; lpm_counter:scan_cnt_rtl_0|dffs[3], lpm_counter:scan_cnt_rtl_0|dffs[2] ; keyout[1] ;
; A ; LC5 ; Select~3244, begin_ad, c_st~11, c_st~12, c_st~13, count_ad[3], count_ad[2], count_ad[0], count_ad[1], count_ad[12], adflag, clk200khz ; cpu_read~1050, count_ad[3], count_ad[4], count_ad[5], count_ad[6], count_ad[7], count_ad[8], count_ad[9], count_ad[12], count_ad[10], count_ad[11], Select~3244, Select~3248, Select~3252, Select~3256, Select~3260, Select~3264, Select~3268, Select~3272, Select~3275, Select~3279 ;
; A ; LC6 ; lpm_counter:scan_cnt_rtl_0|dffs[3], lpm_counter:scan_cnt_rtl_0|dffs[2] ; keyout[3] ;
; A ; LC4 ; c_st~11, c_st~12, count_ad[3], count_ad[2], count_ad[0], count_ad[1], count_ad[12], adflag ; count_ad[3] ;
; A ; LC12 ; lpm_counter:count_rtl_1|dffs[5], lpm_counter:count_rtl_1|dffs[4], lpm_counter:count_rtl_1|dffs[3], lpm_counter:count_rtl_1|dffs[2], lpm_counter:count_rtl_1|dffs[1], lpm_counter:count_rtl_1|dffs[0], reset, clk2mhz ; lpm_counter:count_rtl_1|dffs[7], lpm_counter:count_rtl_1|dffs[8], lpm_counter:count_rtl_1|dffs[9], lpm_counter:count_rtl_1|dffs[10], lpm_counter:count_rtl_1|dffs[11], pwm_pina~reg0, LessThan~667sexp, LessThan~689 ;
; A ; LC7 ; databus[7], pwm_count[7], wr, port_no[0], port_no[1], cs, port_no[2], pwm_count~162sexp ; pwm_count[7], pwm_pina~reg0, LessThan~652sexp, LessThan~688 ;
; A ; LC15 ; clk8mhz, clk2mhz, \divider:count_divider[3], \divider:count_divider[2], \divider:count_divider[0], \divider:count_divider[4] ; \divider:count_divider[0], clk2mhz, \divider:count_divider[2], \divider:count_divider[3], \divider:count_divider[4], clk200khz ;
; A ; LC16 ; cs, port_no[2], rd, port_no[0], port_no[1] ; databus[0], databus[1], databus[2], databus[3], databus[4], databus[5], databus[6], databus[7] ;
; B ; LC19 ; databus[6], outpa[6]~reg0, wr, cs, port_no[0], port_no[2], port_no[1], cpu_write~23sexp ; outpa[6]~reg0, outpa[6] ⌨️ 快捷键说明
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