music_freq.vhd

本源码设计了自动电子琴

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity music_freq is 
Port ( clk,Auto: in std_logic;
index2 : in std_logic_vector(7 downto 0);     
index0 : out std_logic_vector(7 downto 0)); 
end music_freq;
architecture Behavioral of music_freq is 
signal count0:integer range 0 to 8;
signal count5:integer range 0 to  2;
begin 
process(Auto)
begin
if(Auto'event and Auto='0')then
if count5=2 then
count5<=0;
else count5<=count5+1;
end if ;
end if;
end process;
process(clk)                  
 begin 
   if clk'event and clk='1' then 
if count0=7 then count0<=0;

     else count0<=count0+1; 
      end if; 
   end if; 
end process; 
process(count0,count5,index2)       
begin 
if count5=1 then
   case count0 is                    
   when 0 => index0<="11111110";  
   when 1 => index0<="11111101";
   when 2 => index0<="11111011";
   when 3=> index0<="11110111"; 
   when 4 => index0<="11101111";
   when 5 => index0<="11011111";
   when 6 => index0<="10111111";
   when 7 => index0<="01111111";  
   when others =>index0<="11111111";   
   end case; 
    else 
   index0<=index2;                          
  end if; 
  end process; 
  end Behavioral;