📄 automusic.rpt
字号:
Project Information d:\maxplus2\biancheng\vhdl\automusic.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/19/2007 21:56:42
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
AUTOMUSIC
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
automusic
EPM7032LC44-6 10 8 0 21 15 65 %
User Pins: 10 8 0
Project Information d:\maxplus2\biancheng\vhdl\automusic.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information d:\maxplus2\biancheng\vhdl\automusic.rpt
** FILE HIERARCHY **
|lpm_add_sub:123|
|lpm_add_sub:123|addcore:adder|
|lpm_add_sub:123|addcore:adder|addcore:adder0|
|lpm_add_sub:123|altshift:result_ext_latency_ffs|
|lpm_add_sub:123|altshift:carry_ext_latency_ffs|
|lpm_add_sub:123|altshift:oflow_ext_latency_ffs|
Device-Specific Information: d:\maxplus2\biancheng\vhdl\automusic.rpt
automusic
***** Logic for device 'automusic' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
i i E E
n n S S
d d E E
e e A R R
x x u V G G G c G V V
2 2 t C N N N l N E E
1 0 o C D D D k D D D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
index22 | 7 39 | RESERVED
index23 | 8 38 | RESERVED
index24 | 9 37 | RESERVED
GND | 10 36 | RESERVED
index25 | 11 35 | VCC
index26 | 12 EPM7032LC44-6 34 | index05
index27 | 13 33 | RESERVED
index07 | 14 32 | RESERVED
VCC | 15 31 | RESERVED
index06 | 16 30 | GND
index03 | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
i R R R G V i i R R i
n E E E N C n n E E n
d S S S D C d d S S d
e E E E e e E E e
x R R R x x R R x
0 V V V 0 0 V V 0
2 E E E 1 4 E E 0
D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\maxplus2\biancheng\vhdl\automusic.rpt
automusic
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 5/16( 31%) 13/16( 81%) 8/16( 50%) 12/36( 33%)
B: LC17 - LC32 16/16(100%) 4/16( 25%) 13/16( 81%) 17/36( 47%)
Total dedicated input pins used: 1/4 ( 25%)
Total I/O pins used: 17/32 ( 53%)
Total logic cells used: 21/32 ( 65%)
Total shareable expanders used: 15/32 ( 46%)
Total Turbo logic cells used: 21/32 ( 65%)
Total shareable expanders not available (n/a): 6/32 ( 18%)
Average fan-in: 6.19
Total fan-in: 130
Total input pins required: 10
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 21
Total flipflops required: 7
Total product terms required: 81
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 15
Synthesized logic cells: 1/ 32 ( 3%)
Device-Specific Information: d:\maxplus2\biancheng\vhdl\automusic.rpt
automusic
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 0 1 Auto
43 - - INPUT G 0 0 0 0 0 0 0 clk
5 (2) (A) INPUT 0 0 0 0 0 1 0 index20
6 (3) (A) INPUT 0 0 0 0 0 1 0 index21
7 (4) (A) INPUT 0 0 0 0 0 1 0 index22
8 (5) (A) INPUT 0 0 0 0 0 1 0 index23
9 (6) (A) INPUT 0 0 0 0 0 1 0 index24
11 (7) (A) INPUT 0 0 0 0 0 1 0 index25
12 (8) (A) INPUT 0 0 0 0 0 1 0 index26
13 (9) (A) INPUT 0 0 0 0 0 1 0 index27
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\maxplus2\biancheng\vhdl\automusic.rpt
automusic
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
28 28 B OUTPUT t 6 0 1 1 7 0 0 index00
24 32 B OUTPUT t 4 0 1 1 7 0 0 index01
18 13 A OUTPUT t 4 0 1 1 7 0 0 index02
17 12 A OUTPUT t 4 0 1 1 7 0 0 index03
25 31 B OUTPUT t 2 0 1 1 8 0 0 index04
34 23 B OUTPUT t 0 0 0 1 7 0 0 index05
16 11 A OUTPUT t 0 0 0 1 1 0 0 index06
14 10 A OUTPUT t 0 0 0 1 1 0 0 index07
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\biancheng\vhdl\automusic.rpt
automusic
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(26) 30 B SOFT t 0 0 0 0 2 0 1 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node1
(33) 24 B SOFT t 0 0 0 0 3 0 1 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node2
(32) 25 B SOFT t 0 0 0 0 4 0 1 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node3
(27) 29 B SOFT t 0 0 0 0 5 0 1 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node4
(31) 26 B SOFT t 0 0 0 0 6 0 1 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node5
(7) 4 A TFFE t 0 0 0 1 0 8 7 count5 (:19)
(41) 17 B DFFE + t 0 0 0 0 8 6 7 count05 (:20)
(36) 22 B DFFE + t 0 0 0 0 8 6 8 count04 (:21)
(37) 21 B DFFE + t 0 0 0 0 8 6 9 count03 (:22)
(38) 20 B DFFE + t 0 0 0 0 8 6 10 count02 (:23)
(39) 19 B DFFE + t 0 0 0 0 8 6 11 count01 (:24)
(40) 18 B DFFE + t 0 0 0 0 2 6 12 count00 (:25)
(29) 27 B SOFT s t 1 0 1 0 7 1 0 ~3614~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\biancheng\vhdl\automusic.rpt
automusic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------- LC13 index02
| +------- LC12 index03
| | +----- LC11 index06
| | | +--- LC10 index07
| | | | +- LC4 count5
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'A'
LC | | | | | | A B | Logic cells that feed LAB 'A':
LC4 -> * * * * * | * * | <-- count5
Pin
4 -> - - - - * | * - | <-- Auto
43 -> - - - - - | - - | <-- clk
7 -> * - - - - | * - | <-- index22
8 -> - * - - - | * - | <-- index23
12 -> - - * - - | * - | <-- index26
13 -> - - - * - | * - | <-- index27
LC17 -> * * - - - | * * | <-- count05
LC22 -> * * - - - | * * | <-- count04
LC21 -> * * - - - | * * | <-- count03
LC20 -> * * - - - | * * | <-- count02
LC19 -> * * - - - | * * | <-- count01
LC18 -> * * - - - | * * | <-- count00
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\maxplus2\biancheng\vhdl\automusic.rpt
automusic
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC28 index00
| +----------------------------- LC32 index01
| | +--------------------------- LC31 index04
| | | +------------------------- LC23 index05
| | | | +----------------------- LC30 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node1
| | | | | +--------------------- LC24 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node2
| | | | | | +------------------- LC25 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node3
| | | | | | | +----------------- LC29 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node4
| | | | | | | | +--------------- LC26 |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node5
| | | | | | | | | +------------- LC17 count05
| | | | | | | | | | +----------- LC22 count04
| | | | | | | | | | | +--------- LC21 count03
| | | | | | | | | | | | +------- LC20 count02
| | | | | | | | | | | | | +----- LC19 count01
| | | | | | | | | | | | | | +--- LC18 count00
| | | | | | | | | | | | | | | +- LC27 ~3614~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC30 -> - - - - - - - - - - - - - * - - | - * | <-- |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node1
LC24 -> - - - - - - - - - - - - * - - - | - * | <-- |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node2
LC25 -> - - - - - - - - - - - * - - - - | - * | <-- |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node3
LC29 -> - - - - - - - - - - * - - - - - | - * | <-- |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node4
LC26 -> - - - - - - - - - * - - - - - - | - * | <-- |LPM_ADD_SUB:123|addcore:adder|addcore:adder0|result_node5
LC17 -> * * * * - - - - * * * * * * - * | * * | <-- count05
LC22 -> * * * * - - - * * * * * * * - * | * * | <-- count04
LC21 -> * * * * - - * * * * * * * * - * | * * | <-- count03
LC20 -> * * * * - * * * * * * * * * - * | * * | <-- count02
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -