tone.rpt

本源码设计了自动电子琴

         #  index0 &  index1 & !index2 &  index3 &  index4 &  index5 & 
              index6 &  index7 &  _LC7_B2 & !_LC10_C1;
  _EQ013 =  _LC7_B2 & !_LC10_C1;

-- Node name is ':992' 
-- Equation name is '_LC11_B2', type is buried 
_LC11_B2 = LCELL( _EQ014 $ !_LC15_C1);
  _EQ014 =  index0 &  index1 & !index2 &  index3 &  index4 &  index5 & 
              index6 &  index7 &  _LC7_B2 &  _LC15_C1
         #  index0 &  index1 &  index2 & !index3 &  index4 &  index5 & 
              index6 &  index7 &  _LC7_B2 &  _LC15_C1
         #  index0 &  index1 &  index2 &  index3 & !index4 &  index5 & 
              index6 &  index7 & !_LC15_C1
         # !_LC7_B2 & !_LC15_C1;

-- Node name is '~1017~1' 
-- Equation name is '~1017~1', location is LC9_D5, type is buried.
_LC9_D5  = LCELL( _LC2_C1 $  GND);

-- Node name is '~1017~2' 
-- Equation name is '~1017~2', location is LC1_A3, type is buried.
-- synthesized logic cell 
_LC1_A3  = LCELL( _EQ015 $  GND);
  _EQ015 = !index4 & !index5 & !_LC10_C1 & !_LC13_C1 & !_LC15_C1
         #  index4 &  index5 & !_LC10_C1 & !_LC13_C1 & !_LC15_C1;

-- Node name is ':1017' 
-- Equation name is '_LC2_C1', type is buried 
!_LC2_C1 = _LC2_C1~NOT;
_LC2_C1~NOT = LCELL( _EQ016 $ !_LC1_A3);
  _EQ016 =  index0 &  index1 &  index2 & !index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC1_A3 & !_LC13_C1
         #  index0 &  index1 & !index2 &  index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC1_A3 & !_LC13_C1
         # !index0 &  index1 &  index2 &  index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC1_A3
         # !_LC1_A3 & !_LC10_C1 & !_LC13_C1 & !_LC15_C1 &  _X003;
  _X003  = EXP( index0 &  index1 &  index2 &  index3 &  index6 &  index7);

-- Node name is ':1073' 
-- Equation name is '_LC6_C1', type is buried 
_LC6_C1  = LCELL( _EQ017 $  VCC);
  _EQ017 =  _LC10_C1 & !_LC13_C1
         #  index0 &  index1 & !index2 &  index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC13_C1
         # !index0 &  index1 &  index2 &  index3 &  index4 &  index5 & 
              index6 &  index7
         #  index0 &  index1 &  index2 & !index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC13_C1;

-- Node name is ':1098' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = LCELL( _EQ018 $  GND);
  _EQ018 = !index0 &  index1 &  index2 &  index3 &  index4 &  index5 & 
              index6 &  index7
         # !index2 & !index4 & !_LC13_C1 & !_LC15_C1
         #  index2 &  index3 &  index4 & !_LC13_C1 & !_LC15_C1
         # !_LC7_C1 & !_LC13_C1 & !_LC15_C1
         # !index3 & !_LC13_C1 & !_LC15_C1 &  _X004;
  _X004  = EXP( index2 &  index4);

-- Node name is ':1127' 
-- Equation name is '_LC7_B2', type is buried 
_LC7_B2  = LCELL( _EQ019 $  VCC);
  _EQ019 = !index0 &  index1 &  index2 &  index3 &  index4 &  index5 & 
              index6 &  index7
         #  _LC13_C1;

-- Node name is '~1152~1' 
-- Equation name is '~1152~1', location is LC2_A3, type is buried.
-- synthesized logic cell 
_LC2_A3  = LCELL( _EQ020 $  GND);
  _EQ020 =  index0 &  index2 &  index4 &  _LC10_C1
         # !index2 & !index4 &  _LC10_C1;

-- Node name is ':1152' 
-- Equation name is '_LC6_B2', type is buried 
_LC6_B2  = LCELL( _EQ021 $  _EQ022);
  _EQ021 =  index0 &  index1 &  index2 & !index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC2_A3 &  _X005
         # !index0 & !_LC2_A3 &  _LC10_C1 &  _X004 &  _X005
         # !_LC2_A3 &  _LC10_C1 &  _X005 &  _X006
         # !_LC2_A3 & !_LC10_B2 &  _LC13_C1 &  _X005;
  _X005  = EXP( index0 &  index1 &  index2 &  index3 &  index4 & !index5 & 
              index6 &  index7);
  _X004  = EXP( index2 &  index4);
  _X006  = EXP( index1 &  index3 &  index5 &  index6 &  index7);
  _EQ022 = !_LC2_A3 &  _X005;
  _X005  = EXP( index0 &  index1 &  index2 &  index3 &  index4 & !index5 & 
              index6 &  index7);

-- Node name is ':1179' 
-- Equation name is '_LC5_B2', type is buried 
_LC5_B2  = LCELL( _EQ023 $  GND);
  _EQ023 = !index0 &  index1 &  index2 &  index3 &  index4 &  index5 & 
              index6 &  index7
         #  index0 &  index1 &  index2 & !index3 &  index4 &  index5 & 
              index6 &  index7;

-- Node name is ':1208' 
-- Equation name is '_LC4_B2', type is buried 
_LC4_B2  = LCELL( _EQ024 $  GND);
  _EQ024 =  index0 &  index1 &  index2 &  index3 &  index4 & !index5 & 
              index6 &  index7 &  _LC15_B2
         #  index0 &  index1 &  index2 &  index3 & !index4 &  index5 & 
              index6 &  index7 &  _LC15_B2;

-- Node name is ':1260' 
-- Equation name is '_LC3_C1', type is buried 
_LC3_C1  = LCELL( _EQ025 $  GND);
  _EQ025 = !index0 &  index1 &  index2 &  index3 &  index4 &  index5 & 
              index6 &  index7
         #  index0 &  index1 &  index2 & !index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC13_C1
         #  _LC10_C1 & !_LC13_C1 &  _X007;
  _X007  = EXP( index0 &  index1 & !index2 &  index3 &  index4 &  index5 & 
              index6 &  index7);

-- Node name is ':1287' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = LCELL( _EQ026 $  GND);
  _EQ026 = !index0 &  index1 &  index2 &  index3 &  index4 &  index5 & 
              index6 &  index7
         #  _LC10_C1 & !_LC13_C1
         #  index0 &  index1 &  index2 & !index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC13_C1
         #  index0 &  index1 & !index2 &  index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC13_C1
         #  index0 &  index1 &  index2 &  index3 & !index4 &  index5 & 
              index6 &  index7 & !_LC13_C1;

-- Node name is ':1314' 
-- Equation name is '_LC3_B2', type is buried 
_LC3_B2  = LCELL( _EQ027 $  GND);
  _EQ027 =  index0 &  index1 & !index2 &  index3 &  index4 &  index5 & 
              index6 &  index7
         #  _LC10_C1
         # !_LC7_B2;

-- Node name is '~1341~1' 
-- Equation name is '~1341~1', location is LC8_B2, type is buried.
-- synthesized logic cell 
_LC8_B2  = LCELL( _EQ028 $  GND);
  _EQ028 =  index0 &  index1 &  index2 &  index3 & !index4 &  index5 & 
              index6 &  index7;

-- Node name is '~1341~2' 
-- Equation name is '~1341~2', location is LC10_B2, type is buried.
-- synthesized logic cell 
_LC10_B2 = LCELL( _EQ029 $  GND);
  _EQ029 = !index0 &  index1 &  index2 &  index3 &  index4 &  index5 & 
              index6 &  index7;

-- Node name is ':1341' 
-- Equation name is '_LC13_B2', type is buried 
_LC13_B2 = LCELL( _EQ030 $  _EQ031);
  _EQ030 =  index0 &  index1 &  index2 & !index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC8_B2 &  _X005
         #  index0 &  index1 & !index2 &  index3 &  index4 &  index5 & 
              index6 &  index7 & !_LC8_B2 &  _X005
         # !_LC8_B2 & !_LC10_B2 &  _LC15_C1 &  _X005
         # !_LC8_B2 & !_LC10_B2 &  _LC13_C1 &  _X005;
  _X005  = EXP( index0 &  index1 &  index2 &  index3 &  index4 & !index5 & 
              index6 &  index7);
  _EQ031 = !_LC8_B2 &  _X005;
  _X005  = EXP( index0 &  index1 &  index2 &  index3 &  index4 & !index5 & 
              index6 &  index7);



Project Information                        d:\maxplus2\biancheng\vhdl\tone.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX9000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:02
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:01
   Partitioner                            00:00:00
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:07
   --------------------------             --------
   Total Time                             00:00:12


Memory Allocated
-----------------

Peak memory allocated during compilation  = 13,232K