📄 tone.rpt
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Project Information d:\maxplus2\biancheng\vhdl\tone.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/19/2007 21:54:26
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
TONE
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
tone EPM9320LC84-15 8 22 0 30 17 9 %
User Pins: 8 22 0
Device-Specific Information: d:\maxplus2\biancheng\vhdl\tone.rpt
tone
***** Logic for device 'tone' compiled without errors.
Device: EPM9320LC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R R R
E E E E E E E E E
t t i t t i S i i S S S S S S S S
o o c n c o o n E n n E E E E V E E E E
n n o d o n n d R d d R R R R C R R R R
e e d e d G e e e V e e V V V V C V V V V
0 0 e x e N 0 0 x E x x E E E E I E E E E
3 4 2 6 6 D 0 1 7 D 5 4 D D D D O D D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
index3 | 12 74 | RESERVED
index2 | 13 73 | RESERVED
VCCINT | 14 72 | index0
VCCIO | 15 71 | VCCINT
tone09 | 16 70 | GND
tone05 | 17 69 | RESERVED
GND | 18 68 | RESERVED
tone011 | 19 67 | GND
tone08 | 20 66 | RESERVED
VCCINT | 21 65 | RESERVED
tone013 | 22 EPM9320LC84-15 64 | VCCINT
code0 | 23 63 | tone06
GND | 24 62 | tone07
GND | 25 61 | GND
RESERVED | 26 60 | VCCIO
RESERVED | 27 59 | RESERVED
VCCINT | 28 58 | RESERVED
N.C. | 29 57 | VCCINT
#TDO | 30 56 | ^VPP
code3 | 31 55 | #TMS
tone02 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
h c t t V c c i R # # R R R R G R R R R R
i o o o C o o n E T T E E E E N E E E E E
g d n n C d d d S D C S S S S D S S S S S
h e e e I e e e E I K E E E E E E E E E
4 0 0 O 1 5 x R R R R R R R R R R
1 1 1 V V V V V V V V V V
2 0 E E E E E E E E E E
D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\maxplus2\biancheng\vhdl\tone.rpt
tone
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External Shareable
Block Logic Cells Driven Driven Clocks Presets Interconnect Expanders
A3 2/16( 12%) 2/16( 12%) 0/16( 0%) 0/2 0/2 7/33( 21%) 0/16( 0%)
B2 13/16( 81%) 7/16( 43%) 4/16( 25%) 0/2 0/2 12/33( 36%) 7/16( 43%)
C1 13/16( 81%) 9/16( 56%) 2/16( 12%) 0/2 0/2 9/33( 27%) 10/16( 62%)
D4 1/16( 6%) 0/16( 0%) 1/16( 6%) 0/2 0/2 1/33( 3%) 0/16( 0%)
D5 1/16( 6%) 0/16( 0%) 1/16( 6%) 0/2 0/2 1/33( 3%) 0/16( 0%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 26/56 ( 46%)
Total logic cells used: 30/320 ( 9%)
Total shareable expanders used: 8/320 ( 2%)
Total Turbo logic cells used: 30/320 ( 9%)
Total shareable expanders not available (n/a): 9/320 ( 2%)
Average fan-in: 8.83
Total fan-in: 265
Total input pins required: 8
Total input I/O cell registers required: 0
Total output pins required: 22
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total logic cells required: 30
Total flipflops required: 0
Total product terms required: 98
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 7
Total packed registers required: 0
Synthesized logic cells: 6/ 320 ( 1%)
Logic Cell Counts
Column: 01 02 03 04 05 Total
A: 0 0 2 0 0 2
B: 0 13 0 0 0 13
C: 13 0 0 0 0 13
D: 0 0 0 1 1 2
Total: 13 13 2 1 1 30
Device-Specific Information: d:\maxplus2\biancheng\vhdl\tone.rpt
tone
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
72 - - -- INPUT 0 0 0 0 0 0 27 index0
40 - - 03 INPUT 0 0 0 0 0 0 26 index1
13 - - -- INPUT 0 0 0 0 0 0 26 index2
12 - - 01 INPUT 0 0 0 0 0 0 25 index3
84 - - -- INPUT 0 0 0 0 0 0 27 index4
1 - - -- INPUT 0 0 0 0 0 0 27 index5
8 - - 02 INPUT 0 0 0 0 0 0 26 index6
3 - - 03 INPUT 0 0 0 0 0 0 26 index7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\biancheng\vhdl\tone.rpt
tone
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
23 - B -- OUTPUT 0 0 0 0 1 0 0 code0
38 - - 02 OUTPUT 0 0 0 0 1 0 0 code1
9 - - 01 OUTPUT 0 0 0 0 1 0 0 code2
31 - - 01 OUTPUT 0 0 0 0 1 0 0 code3
34 - - 01 OUTPUT 0 0 0 0 1 0 0 code4
39 - - 02 OUTPUT 0 0 0 0 1 0 0 code5
7 - - 02 OUTPUT 0 0 0 0 1 0 0 code6
33 - - 01 OUTPUT 0 0 0 0 1 0 0 high
5 - - 02 OUTPUT 0 0 0 0 1 0 0 tone00
4 - - 02 OUTPUT 0 0 0 0 1 0 0 tone01
32 - - 01 OUTPUT 0 0 0 0 1 0 0 tone02
11 - - 01 OUTPUT 0 0 0 0 1 0 0 tone03
10 - - 01 OUTPUT ! 0 0 0 0 1 0 0 tone04
17 - D -- OUTPUT 0 0 0 0 1 0 0 tone05
63 - B -- OUTPUT 0 0 0 0 1 0 0 tone06
62 - B -- OUTPUT 0 0 0 0 1 0 0 tone07
20 - C -- OUTPUT 0 0 0 0 1 0 0 tone08
16 - D -- OUTPUT 0 0 0 0 1 0 0 tone09
36 - - 02 OUTPUT 0 0 0 0 1 0 0 tone010
19 - C -- OUTPUT 0 0 0 0 1 0 0 tone011
35 - - 02 OUTPUT 0 0 0 0 1 0 0 tone012
22 - B -- OUTPUT 0 0 0 0 1 0 0 tone013
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\maxplus2\biancheng\vhdl\tone.rpt
tone
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
IOC LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
- 15 C 01 OR2 t 0 0 0 8 0 1 9 :658
- 10 C 01 XOR t ! 0 0 0 8 0 1 14 :678
- 13 C 01 OR2 t 0 0 0 8 0 1 14 :778
- 15 B 02 XOR t 0 0 0 8 2 1 2 :803
- 1 B 02 XOR t 0 0 0 8 3 1 0 :828
- 11 C 01 XOR t 0 0 0 8 1 1 0 :857
- 2 B 02 OR2 t 0 0 0 8 4 1 0 :884
- 11 D 04 OR2 t 0 0 0 0 1 1 0 ~909~1
- 8 C 01 SOFT s t 0 0 0 8 3 0 1 ~909~2
- 1 C 01 XOR t ! 2 0 1 8 4 0 1 :909
- 7 C 01 SOFT s t 0 0 0 5 0 0 2 ~936~1
- 9 C 01 OR2 t 2 0 1 8 3 1 0 :936
- 9 B 02 XOR t 1 0 1 8 2 1 0 :965
- 11 B 02 AND2 t 1 0 1 8 2 1 0 :992
- 9 D 05 OR2 t 0 0 0 0 1 1 0 ~1017~1
- 1 A 03 SOFT s t 0 0 0 2 3 0 1 ~1017~2
- 2 C 01 XOR t ! 2 0 1 8 4 0 1 :1017
- 6 C 01 XOR t 0 0 0 8 2 1 0 :1073
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