📄 zongtu4.rpt
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Project Information d:\maxplus2\biancheng\vhdl\zongtu4.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 01/19/2007 19:57:45
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
zongtu4 EPM9320LC84-15 11 9 0 92 45 28 %
User Pins: 11 9 0
Project Information d:\maxplus2\biancheng\vhdl\zongtu4.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk4hz' chosen for auto global Clock
INFO: Signal 'clk12mhz' chosen for auto global Clock
Project Information d:\maxplus2\biancheng\vhdl\zongtu4.rpt
** FILE HIERARCHY **
|automusic:1|
|automusic:1|lpm_add_sub:123|
|automusic:1|lpm_add_sub:123|addcore:adder|
|automusic:1|lpm_add_sub:123|addcore:adder|addcore:adder0|
|automusic:1|lpm_add_sub:123|altshift:result_ext_latency_ffs|
|automusic:1|lpm_add_sub:123|altshift:carry_ext_latency_ffs|
|automusic:1|lpm_add_sub:123|altshift:oflow_ext_latency_ffs|
|speaker:2|
|speaker:2|lpm_add_sub:126|
|speaker:2|lpm_add_sub:126|addcore:adder|
|speaker:2|lpm_add_sub:126|addcore:adder|addcore:adder1|
|speaker:2|lpm_add_sub:126|addcore:adder|addcore:adder0|
|speaker:2|lpm_add_sub:126|altshift:result_ext_latency_ffs|
|speaker:2|lpm_add_sub:126|altshift:carry_ext_latency_ffs|
|speaker:2|lpm_add_sub:126|altshift:oflow_ext_latency_ffs|
|tone:3|
Device-Specific Information: d:\maxplus2\biancheng\vhdl\zongtu4.rpt
zongtu4
***** Logic for device 'zongtu4' compiled without errors.
Device: EPM9320LC84-15
Device Options:
Turbo Bit = ON
Security Bit = OFF
User Code = ffff
MultiVolt I/O = OFF
R R R R R R R c R R R R R R R R
i i E E E E E E E l E E E E E E E E
n n S S S S S S S k c S S S S S S S S
d d E E E E E E E 1 l E E E E V E E E E
e e R R R R R R R 2 k R R R R C R R R R
x x V V V G V V V V m 4 V V V V C V V V V
2 2 E E E N E E E E h h E E E E I E E E E
2 0 D D D D D D D D z z D D D D O D D D D
-----------------------------------------------------------------_
/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |
index26 | 12 74 | RESERVED
index23 | 13 73 | RESERVED
VCCINT | 14 72 | index24
VCCIO | 15 71 | VCCINT
code3 | 16 70 | GND
code5 | 17 69 | RESERVED
GND | 18 68 | RESERVED
code1 | 19 67 | GND
high | 20 66 | RESERVED
VCCINT | 21 65 | RESERVED
spk | 22 EPM9320LC84-15 64 | VCCINT
auto | 23 63 | code0
GND | 24 62 | code2
GND | 25 61 | GND
code4 | 26 60 | VCCIO
RESERVED | 27 59 | RESERVED
VCCINT | 28 58 | RESERVED
N.C. | 29 57 | VCCINT
#TDO | 30 56 | ^VPP
index25 | 31 55 | #TMS
index27 | 32 54 | RESERVED
|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|
------------------------------------------------------------------
i c R R V R R R R # # R R R R G R R R R R
n o E E C E E E E T T E E E E N E E E E E
d d S S C S S S S D C S S S S D S S S S S
e e E E I E E E E I K E E E E E E E E E
x 6 R R O R R R R R R R R R R R R R
2 V V V V V V V V V V V V V V V
1 E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
Device-Specific Information: d:\maxplus2\biancheng\vhdl\zongtu4.rpt
zongtu4
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External Shareable
Block Logic Cells Driven Driven Clocks Presets Interconnect Expanders
A3 1/16( 6%) 0/16( 0%) 1/16( 6%) 0/2 0/2 9/33( 27%) 0/16( 0%)
A4 14/16( 87%) 6/16( 37%) 2/16( 12%) 0/2 0/2 24/33( 72%) 10/16( 62%)
A5 10/16( 62%) 4/16( 25%) 0/16( 0%) 0/2 0/2 31/33( 93%) 7/16( 43%)
B1 13/16( 81%) 12/16( 75%) 0/16( 0%) 0/2 0/2 3/33( 9%) 1/16( 6%)
B3 3/16( 18%) 0/16( 0%) 2/16( 12%) 0/2 0/2 5/33( 15%) 0/16( 0%)
B4 2/16( 12%) 0/16( 0%) 1/16( 6%) 0/2 0/2 1/33( 3%) 0/16( 0%)
C2 13/16( 81%) 7/16( 43%) 2/16( 12%) 0/2 0/2 33/33(100%) 8/16( 50%)
C5 12/16( 75%) 4/16( 25%) 5/16( 31%) 0/2 0/2 22/33( 66%) 10/16( 62%)
D2 4/16( 25%) 1/16( 6%) 1/16( 6%) 0/2 0/2 17/33( 51%) 2/16( 12%)
D3 16/16(100%) 6/16( 37%) 4/16( 25%) 0/2 0/2 28/33( 84%) 7/16( 43%)
D4 4/16( 25%) 2/16( 12%) 2/16( 12%) 0/2 0/2 9/33( 27%) 0/16( 0%)
Total dedicated input pins used: 4/4 (100%)
Total I/O pins used: 16/56 ( 28%)
Total logic cells used: 92/320 ( 28%)
Total shareable expanders used: 14/320 ( 4%)
Total Turbo logic cells used: 92/320 ( 28%)
Total shareable expanders not available (n/a): 31/320 ( 9%)
Average fan-in: 12.38
Total fan-in: 1139
Total input pins required: 11
Total input I/O cell registers required: 0
Total output pins required: 9
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total logic cells required: 92
Total flipflops required: 24
Total product terms required: 308
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 14
Total packed registers required: 0
Synthesized logic cells: 37/ 320 ( 11%)
Logic Cell Counts
Column: 01 02 03 04 05 Total
A: 0 0 1 14 10 25
B: 13 0 3 2 0 18
C: 0 13 0 0 12 25
D: 0 4 16 4 0 24
Total: 13 17 20 20 22 92
Device-Specific Information: d:\maxplus2\biancheng\vhdl\zongtu4.rpt
zongtu4
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
23 - B -- INPUT 0 0 0 0 0 0 1 auto
84 - - -- INPUT G 0 0 0 0 0 0 0 clk4hz
1 - - -- INPUT G 0 0 0 0 0 0 0 clk12mhz
10 - - 01 INPUT 0 0 0 0 0 0 32 index20
33 - - 01 INPUT 0 0 0 0 0 0 32 index21
11 - - 01 INPUT 0 0 0 0 0 0 32 index22
13 - - -- INPUT 0 0 0 0 0 0 32 index23
72 - - -- INPUT 0 0 0 0 0 0 32 index24
31 - - 01 INPUT 0 0 0 0 0 0 32 index25
12 - - 01 INPUT 0 0 0 0 0 0 32 index26
32 - - 01 INPUT 0 0 0 0 0 0 32 index27
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: d:\maxplus2\biancheng\vhdl\zongtu4.rpt
zongtu4
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC Row Col Primitive Code Total Shared n/a INP FBK OUT FBK Name
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