control.vhd

本源码设计了自动电子琴

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity control is
port(clk:in std_logic;
          q:out integer range 0 to 16383 );
end;
architecture one of control is
type mystate is(s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,
                s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,
                s20,s21,s22,s23,s24,s25,s26,s27,s28,s29);
signal state:mystate;
begin
process(clk)
begin
if clk'event and clk='1' then
case state is
when s0=>q<=7281;state<=s1;--low 3
when s1=>q<=7281;state<=s2;--low 3
when s2=>q<=7281;state<=s3;--low 3
when s3=>q<=7281;state<=s4;--low 3
when s4=>q<=8730;state<=s5;--low 5
when s5=>q<=8730;state<=s6;--low 5
when s6=>q<=8730;state<=s7;--low 5
when s7=>q<=9565;state<=s8;--low 6
when s8=>q<=10647;state<=s9;--mid 1
when s9=>q<=10647;state<=s10;--mid 1
when s10=>q<=10647;state<=s11;--mid 1
when s11=>q<=11272;state<=s12;--mid 2
when s12=>q<=9565;state<=s13;--low 6
when s13=>q<=10647;state<=s14;--mid 1
when s14=>q<=8730;state<=s15;--low 5
when s15=>q<=8730;state<=s16;--low 5
when s16=>q<=10647;state<=s17;--mid 1
when s17=>q<=10647;state<=s18;--mid 1
when s18=>q<=12556;state<=s19;--mid 5
when s19=>q<=10647;state<=s20;--hig 1
when s20=>q<=12974;state<=s21;--mid 6
when s21=>q<=12556;state<=s22;--mid 5
when s22=>q<=11831;state<=s23;--mid 3
when s23=>q<=12556;state<=s24;--mid 5
when s24=>q<=11272;state<=s25;--mid 2
when s25=>q<=11272;state<=s26;--mid 2
when s26=>q<=11272;state<=s27;--mid 2
when s27=>q<=11272;state<=s28;--mid 2
when s28=>q<=11272;state<=s29;--mid 2
when s29=>q<=11272;state<=s0;--mid 2
when others=>state<=s0;
end case;
end if;
end process;
end;