cntrl.vhd

本源码设计了自动电子琴

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cntrl is
port(clk,x1,x0:in std_logic;
        z,en1,en0:out std_logic );
end;
architecture one of cntrl is
type mystate is(s0,s1);
signal state:mystate;
begin
process(clk)
begin
if clk'event and clk='1' then
case state is
when s0=>if x1='1' then state<=s1;else state<=s0;end if;
when s1=>if x0='1' then state<=s0;else state<=s1;end if;
end case;
end if;
end process;
process(state)
begin
case state is
when s0=>z<='1';en1<='1';en0<='0';
when s1=>z<='0';en1<='0';en0<='1';
end case;
end process;
end;