aa_adder.xco

智能天线自适应LMS算法

# BEGIN Project Options
SET flowvendor = Foundation_iSE
SET vhdlsim = True
SET verilogsim = True
SET workingdirectory = D:\work\ISE\c11
SET speedgrade = -12
SET simulationfiles = Behavioral
SET asysymbol = True
SET addpads = False
SET device = xc4vsx35
SET implementationfiletype = Edif
SET busformat = BusFormatAngleBracketNotRipped
SET foundationsym = False
SET package = ff668
SET createndf = False
SET designentry = VHDL
SET devicefamily = virtex4
SET formalverification = False
SET removerpms = False
# END Project Options
# BEGIN Select
SELECT Accumulator family Xilinx,_Inc. 7.0
# END Select
# BEGIN Parameters
CSET create_rpm=true
CSET output_width=16
CSET async_init_value=0
CSET saturate=false
CSET clock_enable=false
CSET bypass=true
CSET asynchronous_settings=none
CSET ce_overrides=sync_controls_override_ce
CSET ce_override_for_bypass=false
CSET set_clear_priority=clear_overrides_set
CSET overflow_output=false
CSET port_b_width=16
CSET port_b_constant_value=0
CSET component_name=aa_adder
CSET carry_borrow_output=false
CSET port_a_feedback_scaling=0
CSET operation=add
CSET carry_borrow_input=false
CSET bypass_sense=active_high
CSET output_options=registered
CSET port_b_constant=false
CSET sync_init_value=0
CSET port_b_sign=unsigned
# END Parameters
GENERATE