vgax.vhd

基于FPGA的VGA显示驱动源码~适合哪些想要开发VGA接口驱动的朋友

library ieee;
use ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity vgainterface is
	port(
		reset					:	in	std_logic;
		clock0 					:	in  std_logic;	
		clock2					:	in  std_logic;
--		time_output				:  	in  std_logic_vector(23 downto 0);
		vga_hs_control			:	out std_logic;
		vga_vs_control			:	out std_logic;
		vga_read_dispaly 		:	out std_logic; 
		vga_green_dispaly		:	out std_logic;
		vga_blue_dispaly		:	out std_logic		
	);
end VgaInterface;	 

architecture vgainterface of vgainterface is
-------------------------------------------------------------------
component tsinghua is
	port(
		address		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
		inclock		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
	);
end component;
--------------------------------------------------------------------
signal 	clock_25mhz		: 	std_logic;
signal 	vga_h_sync		: 	std_logic;
signal 	vga_v_sync		: 	std_logic;
signal 	vga_read		: 	std_logic; 
signal 	vga_green		: 	std_logic;
signal 	vga_blue		: 	std_logic;
signal 	count_x			: 	std_logic_vector(9 downto 0);	  
signal 	count_y			: 	std_logic_vector(8 downto 0);
signal 	count_z			: 	std_logic_vector(4 downto 0);	
---------------------------------------------------------------------
signal	address			:	std_logic_vector(13 DOWNTO 0);
signal  q				:	std_logic_vector(0 DOWNTO 0);
---------------------------------------------------------------------  

begin 
--------------------------------------
u1:	tsinghua port map(
		address,
		clock0,	
		q		
	);
	
	process(reset,clock2)
	begin 
		if reset='0' then 
			count_z <= (others=>'0');
		elsif(clock2'event and clock2='1')then		
			if count_z=21 then
				count_z <= (others=>'0');
			else
				count_z <= count_z+1 ;
			end if;	
		end if;
	end process;
--------------------------------------	
	process(reset,clock0)
	begin	
		if reset='0' then
			clock_25mhz <='0';
		elsif(clock0'event and clock0='1')then	 
			clock_25mhz <= not clock_25mhz;
		end if;
	end process;
	
	process(reset,clock_25mhz)
	begin 
		if reset='0' then 
			count_x <= (others=>'0');
		elsif(clock_25mhz'event and clock_25mhz='1')then		
			if count_x=799 then
				count_x <= (others=>'0');
			else
				count_x <= count_x+1 ;
			end if;	
		end if;
	end process;

	process(reset,clock_25mhz)
	begin 
		if reset='0' then 
			count_y <= (others=>'0');
		elsif(clock_25mhz'event and clock_25mhz='1')then
			if count_x=799 then
				if count_y=482 then
					count_y <= (others=>'0');
				else
					count_y <= count_y+1 ;
				end if;		
			end if;
		end if;
	end process;   	
	
	process(reset,clock_25mhz)
	begin	
		if reset='0' then
			vga_h_sync <= '0';	
		elsif(clock_25mhz'event and clock_25mhz='1')then
			if(count_x<640)then 
				vga_h_sync <= '1'; 
			else
				vga_h_sync <= '0';	
			end if;
		end if;
	end process;  

	process(reset,clock_25mhz)
	begin	
		if reset='0' then
			vga_v_sync <= '0'; 
		elsif(clock_25mhz'event and clock_25mhz='1')then
			if(count_y<480)then 
				vga_v_sync <= '1';	
			else	
				vga_v_sync <= '0'; 
			end if;
		end if;
	end process;   
 
	process(reset,clock_25mhz)
	begin 
		if reset='0'then
			vga_hs_control <= '0';
			vga_vs_control <= '0';	
		elsif(clock_25mhz'event and clock_25mhz='1')then
			vga_hs_control <= vga_h_sync;
			vga_vs_control <= vga_v_sync;
		end if;
	end process;
	
	process(reset,clock_25mhz)
	begin 
		if reset='0' then
			vga_read_dispaly	<= '0';
		elsif(clock_25mhz'event and clock_25mhz='1')then 
			vga_read_dispaly	<=vga_read and vga_h_sync and vga_v_sync;
		end if;
	end process;
	
	process(reset,clock_25mhz)
	begin 
		if reset='0' then
			vga_green_dispaly	<= '0';
		elsif(clock_25mhz'event and clock_25mhz='1')then 
			vga_green_dispaly	<=vga_green and vga_h_sync and vga_v_sync; 
		end if;
	end process;
	
	process(reset,clock_25mhz)
	begin 
		if reset='0' then
			vga_blue_dispaly	<= '0';
		elsif(clock_25mhz'event and clock_25mhz='1')then 
			vga_blue_dispaly	<=vga_blue and vga_h_sync and vga_v_sync; 
		end if;
	end process;
		
	process(reset,clock_25mhz)
	begin  
		if reset='0' then
			vga_read	<= '0';
			vga_green	<= '0';
			vga_blue	<= '0';		
		elsif(clock_25mhz'event and clock_25mhz='1')then 
			if count_x>192 and count_x<448 then
				if 	count_x<448 then
					if count_z>0 and count_z<4 then
						vga_read	<= '0';
						vga_green	<= '0';
						vga_blue	<= q(0);	
					elsif (count_z>4 or count_z=4)and count_z<7 then
						vga_read	<= '0';
						vga_green	<= q(0);
						vga_blue	<= '0';
					elsif (count_z>7 or count_z=7)and count_z<10 then
						vga_read	<= '0';
						vga_green	<= q(0);
						vga_blue	<= q(0);
					elsif (count_z>10 or count_z=10)and count_z<13 then
						vga_read	<= q(0);
						vga_green	<= '0';
						vga_blue	<= '0';
					elsif (count_z>13 or count_z=13)and count_z<16 then
						vga_read	<= q(0);
						vga_green	<= '0';
						vga_blue	<= q(0);
					elsif (count_z>16 or count_z=16)and count_z<19 then
						vga_read	<= q(0);
						vga_green	<= q(0);
						vga_blue	<= '0';
					else 
						vga_read	<= q(0);
						vga_green	<= q(0);
						vga_blue	<= q(0);					
					end if;																																										 
				else
					vga_read	<= '0';
					vga_green	<= '0';
					vga_blue	<= '0';
				end if;
			end if;
		end if;
	end process;
	
	process(reset,clock_25mhz)
	begin
		if reset='0' then
			address <= (others=>'0');
		elsif(clock_25mhz'event and clock_25mhz='1')then 
			if  count_y>128 and count_y<384 then
				if 	count_x>192 and count_x<448 then
					address(6 downto 0)<=count_x(7 downto 1)-96;
					address(13 downto 7)<=count_y(7 downto 1)-64;
				end if;
			end if;
		end if;
	end process;
	
end vgainterface;