crc16_d8_m.v

crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a ver

///////////////////////////////////////////////////////////////////////
// File:  CRC16_D8.v                             
// Date:  Fri Jun  6 09:08:25 2008                                                      
//                                                                     
// Copyright (C) 1999-2003 Easics NV.                 
// This source file may be used and distributed without restriction    
// provided that this copyright statement is not removed from the file 
// and that any derivative work contains the original copyright notice
// and the associated disclaimer.
//
// THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
// OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
// WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
//
// Purpose: Verilog module containing a synthesizable CRC function
//   * polynomial: (0 5 12 16)
//   * data width: 8
//                                                                     
// Info: [e-mail]
//       http://www.easics.com                                  
///////////////////////////////////////////////////////////////////////


module CRC16_D8( input clk,
	         input rst_n,
		 input [7:0] D,
		 input d_valid,
		 output reg [15:0] C
		 );

  // polynomial: (0 5 12 16)
  // data width: 8
  // convention: the first serial data bit is D[7]
  wire [15:0] NewCRC;
  always @(posedge clk or negedge rst_n)
  begin
    if(~rst_n) 
      C <= 16'hffff;
    else if (d_valid)
      C <= NewCRC;
    else
      C <= C;
  end

 assign  NewCRC[0] = D[4] ^ D[0] ^ C[8] ^ C[12];
 assign  NewCRC[1] = D[5] ^ D[1] ^ C[9] ^ C[13];
 assign  NewCRC[2] = D[6] ^ D[2] ^ C[10] ^ C[14];
 assign  NewCRC[3] = D[7] ^ D[3] ^ C[11] ^ C[15];
 assign  NewCRC[4] = D[4] ^ C[12];
 assign  NewCRC[5] = D[5] ^ D[4] ^ D[0] ^ C[8] ^ C[12] ^ C[13];
 assign  NewCRC[6] = D[6] ^ D[5] ^ D[1] ^ C[9] ^ C[13] ^ C[14];
 assign  NewCRC[7] = D[7] ^ D[6] ^ D[2] ^ C[10] ^ C[14] ^ C[15];
 assign  NewCRC[8] = D[7] ^ D[3] ^ C[0] ^ C[11] ^ C[15];
 assign  NewCRC[9] = D[4] ^ C[1] ^ C[12];
 assign  NewCRC[10] = D[5] ^ C[2] ^ C[13];
 assign  NewCRC[11] = D[6] ^ C[3] ^ C[14];
 assign  NewCRC[12] = D[7] ^ D[4] ^ D[0] ^ C[4] ^ C[8] ^ C[12] ^ C[15];
 assign  NewCRC[13] = D[5] ^ D[1] ^ C[5] ^ C[9] ^ C[13];
 assign  NewCRC[14] = D[6] ^ D[2] ^ C[6] ^ C[10] ^ C[14];
 assign  NewCRC[15] = D[7] ^ D[3] ^ C[7] ^ C[11] ^ C[15];




endmodule