usb.tan.rpt

这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序

+-------+--------------+------------+-------+---------------------------+----------+


+------------------------------------------------------------------------------------------+
; tco                                                                                      ;
+-------+--------------+------------+---------------------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From                      ; To          ; From Clock ;
+-------+--------------+------------+---------------------------+-------------+------------+
; N/A   ; None         ; 9.246 ns   ; USB_T:inst2|Data2USB[6]   ; USB_data[0] ; clk        ;
; N/A   ; None         ; 9.246 ns   ; USB_T:inst2|Data2USB[6]   ; USB_data[2] ; clk        ;
; N/A   ; None         ; 9.246 ns   ; USB_T:inst2|Data2USB[6]   ; USB_data[3] ; clk        ;
; N/A   ; None         ; 9.233 ns   ; USB_T:inst2|TriEnableDout ; USB_data[4] ; clk        ;
; N/A   ; None         ; 9.233 ns   ; USB_T:inst2|TriEnableDout ; USB_data[5] ; clk        ;
; N/A   ; None         ; 9.217 ns   ; USB_T:inst2|TriEnableDout ; USB_data[1] ; clk        ;
; N/A   ; None         ; 9.199 ns   ; USB_T:inst2|Data2USB[6]   ; USB_data[6] ; clk        ;
; N/A   ; None         ; 8.756 ns   ; USB_T:inst2|TriEnableDout ; USB_data[7] ; clk        ;
; N/A   ; None         ; 8.655 ns   ; USB_T:inst2|USB_WR        ; USB_WR      ; clk        ;
; N/A   ; None         ; 8.089 ns   ; USB_T:inst2|TriEnableDout ; USB_data[3] ; clk        ;
; N/A   ; None         ; 8.072 ns   ; USB_T:inst2|TriEnableDout ; USB_data[0] ; clk        ;
; N/A   ; None         ; 8.072 ns   ; USB_T:inst2|TriEnableDout ; USB_data[2] ; clk        ;
; N/A   ; None         ; 7.612 ns   ; USB_T:inst2|TriEnableDout ; USB_data[6] ; clk        ;
+-------+--------------+------------+---------------------------+-------------+------------+


+----------------------------------------------------------------------------------------+
; th                                                                                     ;
+---------------+-------------+-----------+-------+---------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To                        ; To Clock ;
+---------------+-------------+-----------+-------+---------------------------+----------+
; N/A           ; None        ; -1.454 ns ; TXE_n ; USB_T:inst2|Data2USB[6]   ; clk      ;
; N/A           ; None        ; -1.648 ns ; Reset ; USB_T:inst2|State.00001   ; clk      ;
; N/A           ; None        ; -1.650 ns ; Reset ; USB_T:inst2|TriEnableDout ; clk      ;
; N/A           ; None        ; -1.650 ns ; Reset ; USB_T:inst2|Data2USB[6]   ; clk      ;
; N/A           ; None        ; -1.651 ns ; Reset ; USB_T:inst2|State.01000   ; clk      ;
; N/A           ; None        ; -1.654 ns ; Reset ; USB_T:inst2|State.00010   ; clk      ;
; N/A           ; None        ; -1.656 ns ; Reset ; USB_T:inst2|USB_WR        ; clk      ;
; N/A           ; None        ; -1.656 ns ; Reset ; USB_T:inst2|State.00100   ; clk      ;
; N/A           ; None        ; -2.660 ns ; TXE_n ; USB_T:inst2|USB_WR        ; clk      ;
; N/A           ; None        ; -2.660 ns ; TXE_n ; USB_T:inst2|State.00001   ; clk      ;
; N/A           ; None        ; -2.660 ns ; TXE_n ; USB_T:inst2|State.00010   ; clk      ;
; N/A           ; None        ; -2.660 ns ; TXE_n ; USB_T:inst2|State.01000   ; clk      ;
; N/A           ; None        ; -2.660 ns ; TXE_n ; USB_T:inst2|State.00100   ; clk      ;
+---------------+-------------+-----------+-------+---------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Tue Jun 10 15:07:08 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off usb -c usb
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "USB_T:inst2|State.01000" and destination register "USB_T:inst2|USB_WR"
    Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.386 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y7_N0; Fanout = 2; REG Node = 'USB_T:inst2|State.01000'
            Info: 2: + IC(0.979 ns) + CELL(0.511 ns) = 1.490 ns; Loc. = LC_X3_Y7_N6; Fanout = 1; COMB Node = 'USB_T:inst2|USB_WR~286'
            Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.386 ns; Loc. = LC_X3_Y7_N7; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
            Info: Total cell delay = 1.102 ns ( 46.19 % )
            Info: Total interconnect delay = 1.284 ns ( 53.81 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
                Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y7_N7; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
                Info: Total cell delay = 2.081 ns ( 54.49 % )
                Info: Total interconnect delay = 1.738 ns ( 45.51 % )
            Info: - Longest clock path from clock "clk" to source register is 3.819 ns
                Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
                Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y7_N0; Fanout = 2; REG Node = 'USB_T:inst2|State.01000'
                Info: Total cell delay = 2.081 ns ( 54.49 % )
                Info: Total interconnect delay = 1.738 ns ( 45.51 % )
        Info: + Micro clock to output delay of source is 0.376 ns
        Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "USB_T:inst2|USB_WR" (data pin = "TXE_n", clock pin = "clk") is 3.214 ns
    Info: + Longest pin to register delay is 6.700 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_144; Fanout = 2; PIN Node = 'TXE_n'
        Info: 2: + IC(2.738 ns) + CELL(0.914 ns) = 4.784 ns; Loc. = LC_X3_Y7_N5; Fanout = 5; COMB Node = 'USB_T:inst2|USB_WR~288'
        Info: 3: + IC(0.673 ns) + CELL(1.243 ns) = 6.700 ns; Loc. = LC_X3_Y7_N7; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
        Info: Total cell delay = 3.289 ns ( 49.09 % )
        Info: Total interconnect delay = 3.411 ns ( 50.91 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clk" to destination register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y7_N7; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: tco from clock "clk" to destination pin "USB_data[0]" through register "USB_T:inst2|Data2USB[6]" is 9.246 ns
    Info: + Longest clock path from clock "clk" to source register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y7_N4; Fanout = 5; REG Node = 'USB_T:inst2|Data2USB[6]'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 5.051 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y7_N4; Fanout = 5; REG Node = 'USB_T:inst2|Data2USB[6]'
        Info: 2: + IC(2.729 ns) + CELL(2.322 ns) = 5.051 ns; Loc. = PIN_132; Fanout = 0; PIN Node = 'USB_data[0]'
        Info: Total cell delay = 2.322 ns ( 45.97 % )
        Info: Total interconnect delay = 2.729 ns ( 54.03 % )
Info: th for register "USB_T:inst2|Data2USB[6]" (data pin = "TXE_n", clock pin = "clk") is -1.454 ns
    Info: + Longest clock path from clock "clk" to destination register is 3.819 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
        Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X3_Y7_N4; Fanout = 5; REG Node = 'USB_T:inst2|Data2USB[6]'
        Info: Total cell delay = 2.081 ns ( 54.49 % )
        Info: Total interconnect delay = 1.738 ns ( 45.51 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 5.494 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_144; Fanout = 2; PIN Node = 'TXE_n'
        Info: 2: + IC(3.179 ns) + CELL(1.183 ns) = 5.494 ns; Loc. = LC_X3_Y7_N4; Fanout = 5; REG Node = 'USB_T:inst2|Data2USB[6]'
        Info: Total cell delay = 2.315 ns ( 42.14 % )
        Info: Total interconnect delay = 3.179 ns ( 57.86 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 100 megabytes of memory during processing
    Info: Processing ended: Tue Jun 10 15:07:09 2008
    Info: Elapsed time: 00:00:01