usbrefdesign.map.qmsg

这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 10 17:58:32 2008 " "Info: Processing started: Tue Jun 10 17:58:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off USBRefDesign -c USBRefDesign " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USBRefDesign -c USBRefDesign" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "key_down.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file key_down.v" { { "Info" "ISGN_ENTITY_NAME" "1 key_down " "Info: Found entity 1: key_down" {  } { { "key_down.v" "" { Text "F:/ylc627/QuartusProjectWR/key_down.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "USB_T.v(38) " "Warning (10268): Verilog HDL information at USB_T.v(38): Always Construct contains both blocking and non-blocking assignments" {  } { { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 38 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "USB_T.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file USB_T.v" { { "Info" "ISGN_ENTITY_NAME" "1 USB_T " "Info: Found entity 1: USB_T" {  } { { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "USBRefDesign.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file USBRefDesign.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 USBRefDesign " "Info: Found entity 1: USBRefDesign" {  } { { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "USBRefDesign " "Info: Elaborating entity \"USBRefDesign\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "USB_T USB_T:inst2 " "Info: Elaborating entity \"USB_T\" for hierarchy \"USB_T:inst2\"" {  } { { "USBRefDesign.bdf" "inst2" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 136 448 704 264 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "key_down key_down:inst4 " "Info: Elaborating entity \"key_down\" for hierarchy \"key_down:inst4\"" {  } { { "USBRefDesign.bdf" "inst4" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 368 96 192 464 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_bustri0.v 1 1 " "Warning: Using design file lpm_bustri0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_bustri0 " "Info: Found entity 1: lpm_bustri0" {  } { { "lpm_bustri0.v" "" { Text "F:/ylc627/QuartusProjectWR/lpm_bustri0.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_bustri0 lpm_bustri0:inst " "Info: Elaborating entity \"lpm_bustri0\" for hierarchy \"lpm_bustri0:inst\"" {  } { { "USBRefDesign.bdf" "inst" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 248 144 264 304 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/70/quartus/libraries/megafunctions/lpm_bustri.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/lpm_bustri.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_bustri " "Info: Found entity 1: lpm_bustri" {  } { { "lpm_bustri.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/lpm_bustri.tdf" 31 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_bustri lpm_bustri0:inst\|lpm_bustri:lpm_bustri_component " "Info: Elaborating entity \"lpm_bustri\" for hierarchy \"lpm_bustri0:inst\|lpm_bustri:lpm_bustri_component\"" {  } { { "lpm_bustri0.v" "lpm_bustri_component" { Text "F:/ylc627/QuartusProjectWR/lpm_bustri0.v" 60 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_bustri0:inst\|lpm_bustri:lpm_bustri_component " "Info: Elaborated megafunction instantiation \"lpm_bustri0:inst\|lpm_bustri:lpm_bustri_component\"" {  } { { "lpm_bustri0.v" "" { Text "F:/ylc627/QuartusProjectWR/lpm_bustri0.v" 60 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "USB_T:inst2\|USB_WU High " "Info: Power-up level of register \"USB_T:inst2\|USB_WU\" is not specified -- using power-up level of High to minimize register" {  } { { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 22 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}