📄 usbrefdesign.tan.qmsg
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{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "HalfClock_settings " "Warning: Clock Setting \"HalfClock_settings\" is unassigned" { } { } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0}
{ "Warning" "WTAN_CLOCK_SETTING_NOT_USED" "QuarterClock_settings " "Warning: Clock Setting \"QuarterClock_settings\" is unassigned" { } { } 0 0 "Clock Setting \"%1!s!\" is unassigned" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register USB_T:inst2\|State.00010 USB_T:inst2\|USB_WR 304.04 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 304.04 MHz between source register \"USB_T:inst2\|State.00010\" and destination register \"USB_T:inst2\|USB_WR\"" { { "Info" "ITDB_CLOCK_RATE" "clock 3.289 ns " "Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.396 ns + Longest register register " "Info: + Longest register to register delay is 2.396 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns USB_T:inst2\|State.00010 1 REG LC_X4_Y10_N6 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y10_N6; Fanout = 3; REG Node = 'USB_T:inst2\|State.00010'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_T:inst2|State.00010 } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.989 ns) + CELL(0.511 ns) 1.500 ns USB_T:inst2\|USB_WR~286 2 COMB LC_X4_Y10_N1 1 " "Info: 2: + IC(0.989 ns) + CELL(0.511 ns) = 1.500 ns; Loc. = LC_X4_Y10_N1; Fanout = 1; COMB Node = 'USB_T:inst2\|USB_WR~286'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { USB_T:inst2|State.00010 USB_T:inst2|USB_WR~286 } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 2.396 ns USB_T:inst2\|USB_WR 3 REG LC_X4_Y10_N2 2 " "Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.396 ns; Loc. = LC_X4_Y10_N2; Fanout = 2; REG Node = 'USB_T:inst2\|USB_WR'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { USB_T:inst2|USB_WR~286 USB_T:inst2|USB_WR } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.102 ns ( 45.99 % ) " "Info: Total cell delay = 1.102 ns ( 45.99 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.294 ns ( 54.01 % ) " "Info: Total interconnect delay = 1.294 ns ( 54.01 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.396 ns" { USB_T:inst2|State.00010 USB_T:inst2|USB_WR~286 USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.396 ns" { USB_T:inst2|State.00010 USB_T:inst2|USB_WR~286 USB_T:inst2|USB_WR } { 0.000ns 0.989ns 0.305ns } { 0.000ns 0.511ns 0.591ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 7 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 64 -144 24 80 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns USB_T:inst2\|USB_WR 2 REG LC_X4_Y10_N2 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N2; Fanout = 2; REG Node = 'USB_T:inst2\|USB_WR'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk USB_T:inst2|USB_WR } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|USB_WR } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 7 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 64 -144 24 80 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns USB_T:inst2\|State.00010 2 REG LC_X4_Y10_N6 3 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N6; Fanout = 3; REG Node = 'USB_T:inst2\|State.00010'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk USB_T:inst2|State.00010 } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|State.00010 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|State.00010 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|USB_WR } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|State.00010 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|State.00010 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 34 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.396 ns" { USB_T:inst2|State.00010 USB_T:inst2|USB_WR~286 USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.396 ns" { USB_T:inst2|State.00010 USB_T:inst2|USB_WR~286 USB_T:inst2|USB_WR } { 0.000ns 0.989ns 0.305ns } { 0.000ns 0.511ns 0.591ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|USB_WR } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|State.00010 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|State.00010 } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { USB_T:inst2|USB_WR } { } { } "" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "USB_T:inst2\|USB_WR Reset clk 4.982 ns register " "Info: tsu for register \"USB_T:inst2\|USB_WR\" (data pin = \"Reset\", clock pin = \"clk\") is 4.982 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.468 ns + Longest pin register " "Info: + Longest pin to register delay is 8.468 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Reset 1 PIN PIN_42 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 8; PIN Node = 'Reset'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 176 32 200 192 "Reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.919 ns) + CELL(0.511 ns) 6.562 ns USB_T:inst2\|USB_WR~288 2 COMB LC_X4_Y10_N7 5 " "Info: 2: + IC(4.919 ns) + CELL(0.511 ns) = 6.562 ns; Loc. = LC_X4_Y10_N7; Fanout = 5; COMB Node = 'USB_T:inst2\|USB_WR~288'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.430 ns" { Reset USB_T:inst2|USB_WR~288 } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.663 ns) + CELL(1.243 ns) 8.468 ns USB_T:inst2\|USB_WR 3 REG LC_X4_Y10_N2 2 " "Info: 3: + IC(0.663 ns) + CELL(1.243 ns) = 8.468 ns; Loc. = LC_X4_Y10_N2; Fanout = 2; REG Node = 'USB_T:inst2\|USB_WR'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.906 ns" { USB_T:inst2|USB_WR~288 USB_T:inst2|USB_WR } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.886 ns ( 34.08 % ) " "Info: Total cell delay = 2.886 ns ( 34.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.582 ns ( 65.92 % ) " "Info: Total interconnect delay = 5.582 ns ( 65.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.468 ns" { Reset USB_T:inst2|USB_WR~288 USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.468 ns" { Reset Reset~combout USB_T:inst2|USB_WR~288 USB_T:inst2|USB_WR } { 0.000ns 0.000ns 4.919ns 0.663ns } { 0.000ns 1.132ns 0.511ns 1.243ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 7 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 64 -144 24 80 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns USB_T:inst2\|USB_WR 2 REG LC_X4_Y10_N2 2 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N2; Fanout = 2; REG Node = 'USB_T:inst2\|USB_WR'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk USB_T:inst2|USB_WR } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 21 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|USB_WR } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.468 ns" { Reset USB_T:inst2|USB_WR~288 USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.468 ns" { Reset Reset~combout USB_T:inst2|USB_WR~288 USB_T:inst2|USB_WR } { 0.000ns 0.000ns 4.919ns 0.663ns } { 0.000ns 1.132ns 0.511ns 1.243ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|USB_WR } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|USB_WR } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk USB_data\[1\] USB_T:inst2\|TriEnableDout 9.105 ns register " "Info: tco from clock \"clk\" to destination pin \"USB_data\[1\]\" through register \"USB_T:inst2\|TriEnableDout\" is 9.105 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 7 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 64 -144 24 80 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns USB_T:inst2\|TriEnableDout 2 REG LC_X4_Y10_N5 8 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2\|TriEnableDout'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|TriEnableDout } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 23 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.910 ns + Longest register pin " "Info: + Longest register to pin delay is 4.910 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns USB_T:inst2\|TriEnableDout 1 REG LC_X4_Y10_N5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2\|TriEnableDout'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.588 ns) + CELL(2.322 ns) 4.910 ns USB_data\[1\] 2 PIN PIN_133 0 " "Info: 2: + IC(2.588 ns) + CELL(2.322 ns) = 4.910 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'USB_data\[1\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.910 ns" { USB_T:inst2|TriEnableDout USB_data[1] } "NODE_NAME" } } { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 280 -64 112 296 "USB_data\[7..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 47.29 % ) " "Info: Total cell delay = 2.322 ns ( 47.29 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.588 ns ( 52.71 % ) " "Info: Total interconnect delay = 2.588 ns ( 52.71 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.910 ns" { USB_T:inst2|TriEnableDout USB_data[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.910 ns" { USB_T:inst2|TriEnableDout USB_data[1] } { 0.000ns 2.588ns } { 0.000ns 2.322ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|TriEnableDout } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "4.910 ns" { USB_T:inst2|TriEnableDout USB_data[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "4.910 ns" { USB_T:inst2|TriEnableDout USB_data[1] } { 0.000ns 2.588ns } { 0.000ns 2.322ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "USB_T:inst2\|TriEnableDout Reset clk -2.293 ns register " "Info: th for register \"USB_T:inst2\|TriEnableDout\" (data pin = \"Reset\", clock pin = \"clk\") is -2.293 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.819 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.819 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 7 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 64 -144 24 80 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(0.918 ns) 3.819 ns USB_T:inst2\|TriEnableDout 2 REG LC_X4_Y10_N5 8 " "Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2\|TriEnableDout'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.656 ns" { clk USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 54.49 % ) " "Info: Total cell delay = 2.081 ns ( 54.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.738 ns ( 45.51 % ) " "Info: Total interconnect delay = 1.738 ns ( 45.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|TriEnableDout } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" { } { { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 23 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.333 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.333 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns Reset 1 PIN PIN_42 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 8; PIN Node = 'Reset'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { Reset } "NODE_NAME" } } { "USBRefDesign.bdf" "" { Schematic "F:/ylc627/QuartusProjectWR/USBRefDesign.bdf" { { 176 32 200 192 "Reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.921 ns) + CELL(0.280 ns) 6.333 ns USB_T:inst2\|TriEnableDout 2 REG LC_X4_Y10_N5 8 " "Info: 2: + IC(4.921 ns) + CELL(0.280 ns) = 6.333 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2\|TriEnableDout'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.201 ns" { Reset USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "USB_T.v" "" { Text "F:/ylc627/QuartusProjectWR/USB_T.v" 23 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns ( 22.30 % ) " "Info: Total cell delay = 1.412 ns ( 22.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.921 ns ( 77.70 % ) " "Info: Total interconnect delay = 4.921 ns ( 77.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.333 ns" { Reset USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.333 ns" { Reset Reset~combout USB_T:inst2|TriEnableDout } { 0.000ns 0.000ns 4.921ns } { 0.000ns 1.132ns 0.280ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.819 ns" { clk USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.819 ns" { clk clk~combout USB_T:inst2|TriEnableDout } { 0.000ns 0.000ns 1.738ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.333 ns" { Reset USB_T:inst2|TriEnableDout } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "6.333 ns" { Reset Reset~combout USB_T:inst2|TriEnableDout } { 0.000ns 0.000ns 4.921ns } { 0.000ns 1.132ns 0.280ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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