📄 usbrefdesign.tan.rpt
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+----------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+-------+---------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+-------+---------------------------+----------+
; N/A ; None ; -2.293 ns ; Reset ; USB_T:inst2|TriEnableDout ; clk ;
; N/A ; None ; -2.636 ns ; TXE_n ; USB_T:inst2|Data2USB[6] ; clk ;
; N/A ; None ; -2.799 ns ; Reset ; USB_T:inst2|USB_WR ; clk ;
; N/A ; None ; -2.803 ns ; Reset ; USB_T:inst2|State.00001 ; clk ;
; N/A ; None ; -2.812 ns ; Reset ; USB_T:inst2|State.01000 ; clk ;
; N/A ; None ; -2.814 ns ; Reset ; USB_T:inst2|State.00100 ; clk ;
; N/A ; None ; -2.816 ns ; Reset ; USB_T:inst2|State.00010 ; clk ;
; N/A ; None ; -3.114 ns ; Reset ; USB_T:inst2|Data2USB[6] ; clk ;
; N/A ; None ; -3.676 ns ; TXE_n ; USB_T:inst2|USB_WR ; clk ;
; N/A ; None ; -3.676 ns ; TXE_n ; USB_T:inst2|State.00001 ; clk ;
; N/A ; None ; -3.676 ns ; TXE_n ; USB_T:inst2|State.00010 ; clk ;
; N/A ; None ; -3.676 ns ; TXE_n ; USB_T:inst2|State.01000 ; clk ;
; N/A ; None ; -3.676 ns ; TXE_n ; USB_T:inst2|State.00100 ; clk ;
+---------------+-------------+-----------+-------+---------------------------+----------+
+----------------------------------------------------------------------------------------------------------+
; Minimum tco ;
+---------------+------------------+----------------+---------------------------+-------------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From ; To ; From Clock ;
+---------------+------------------+----------------+---------------------------+-------------+------------+
; N/A ; None ; 7.276 ns ; USB_T:inst2|TriEnableDout ; USB_data[6] ; clk ;
; N/A ; None ; 7.960 ns ; USB_T:inst2|TriEnableDout ; USB_data[3] ; clk ;
; N/A ; None ; 7.960 ns ; USB_T:inst2|TriEnableDout ; USB_data[2] ; clk ;
; N/A ; None ; 7.960 ns ; USB_T:inst2|TriEnableDout ; USB_data[0] ; clk ;
; N/A ; None ; 8.386 ns ; USB_T:inst2|Data2USB[6] ; USB_data[6] ; clk ;
; N/A ; None ; 8.418 ns ; USB_T:inst2|TriEnableDout ; USB_data[7] ; clk ;
; N/A ; None ; 8.418 ns ; USB_T:inst2|TriEnableDout ; USB_data[5] ; clk ;
; N/A ; None ; 8.418 ns ; USB_T:inst2|TriEnableDout ; USB_data[4] ; clk ;
; N/A ; None ; 8.922 ns ; USB_T:inst2|USB_WR ; USB_WR ; clk ;
; N/A ; None ; 8.955 ns ; USB_T:inst2|Data2USB[6] ; USB_data[3] ; clk ;
; N/A ; None ; 8.968 ns ; USB_T:inst2|Data2USB[6] ; USB_data[2] ; clk ;
; N/A ; None ; 8.968 ns ; USB_T:inst2|Data2USB[6] ; USB_data[0] ; clk ;
; N/A ; None ; 9.105 ns ; USB_T:inst2|TriEnableDout ; USB_data[1] ; clk ;
+---------------+------------------+----------------+---------------------------+-------------+------------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Ignored Timing Assignments ;
+----------------+-----------------------+------+--------------------------------+-------------+--------------------------------------------------------------------------+
; Option ; Setting ; From ; To ; Entity Name ; Help ;
+----------------+-----------------------+------+--------------------------------+-------------+--------------------------------------------------------------------------+
; Clock Settings ; HalfClock_settings ; ; DivideClock:inst5|HalfClock ; ; No element named DivideClock:inst5|HalfClock was found in the netlist ;
; Clock Settings ; QuarterClock_settings ; ; DivideClock:inst5|QuarterClock ; ; No element named DivideClock:inst5|QuarterClock was found in the netlist ;
+----------------+-----------------------+------+--------------------------------+-------------+--------------------------------------------------------------------------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Jun 10 17:58:42 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off USBRefDesign -c USBRefDesign
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Warning: Clock Setting "HalfClock_settings" is unassigned
Warning: Clock Setting "QuarterClock_settings" is unassigned
Info: Clock "clk" Internal fmax is restricted to 304.04 MHz between source register "USB_T:inst2|State.00010" and destination register "USB_T:inst2|USB_WR"
Info: fmax restricted to clock pin edge rate 3.289 ns. Expand message to see actual delay path.
Info: + Longest register to register delay is 2.396 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y10_N6; Fanout = 3; REG Node = 'USB_T:inst2|State.00010'
Info: 2: + IC(0.989 ns) + CELL(0.511 ns) = 1.500 ns; Loc. = LC_X4_Y10_N1; Fanout = 1; COMB Node = 'USB_T:inst2|USB_WR~286'
Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.396 ns; Loc. = LC_X4_Y10_N2; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
Info: Total cell delay = 1.102 ns ( 45.99 % )
Info: Total interconnect delay = 1.294 ns ( 54.01 % )
Info: - Smallest clock skew is 0.000 ns
Info: + Shortest clock path from clock "clk" to destination register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N2; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: - Longest clock path from clock "clk" to source register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N6; Fanout = 3; REG Node = 'USB_T:inst2|State.00010'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Micro setup delay of destination is 0.333 ns
Info: tsu for register "USB_T:inst2|USB_WR" (data pin = "Reset", clock pin = "clk") is 4.982 ns
Info: + Longest pin to register delay is 8.468 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 8; PIN Node = 'Reset'
Info: 2: + IC(4.919 ns) + CELL(0.511 ns) = 6.562 ns; Loc. = LC_X4_Y10_N7; Fanout = 5; COMB Node = 'USB_T:inst2|USB_WR~288'
Info: 3: + IC(0.663 ns) + CELL(1.243 ns) = 8.468 ns; Loc. = LC_X4_Y10_N2; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
Info: Total cell delay = 2.886 ns ( 34.08 % )
Info: Total interconnect delay = 5.582 ns ( 65.92 % )
Info: + Micro setup delay of destination is 0.333 ns
Info: - Shortest clock path from clock "clk" to destination register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N2; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: tco from clock "clk" to destination pin "USB_data[1]" through register "USB_T:inst2|TriEnableDout" is 9.105 ns
Info: + Longest clock path from clock "clk" to source register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2|TriEnableDout'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Longest register to pin delay is 4.910 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2|TriEnableDout'
Info: 2: + IC(2.588 ns) + CELL(2.322 ns) = 4.910 ns; Loc. = PIN_133; Fanout = 0; PIN Node = 'USB_data[1]'
Info: Total cell delay = 2.322 ns ( 47.29 % )
Info: Total interconnect delay = 2.588 ns ( 52.71 % )
Info: th for register "USB_T:inst2|TriEnableDout" (data pin = "Reset", clock pin = "clk") is -2.293 ns
Info: + Longest clock path from clock "clk" to destination register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2|TriEnableDout'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro hold delay of destination is 0.221 ns
Info: - Shortest pin to register delay is 6.333 ns
Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_42; Fanout = 8; PIN Node = 'Reset'
Info: 2: + IC(4.921 ns) + CELL(0.280 ns) = 6.333 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2|TriEnableDout'
Info: Total cell delay = 1.412 ns ( 22.30 % )
Info: Total interconnect delay = 4.921 ns ( 77.70 % )
Info: Minimum tco from clock "clk" to destination pin "USB_data[6]" through register "USB_T:inst2|TriEnableDout" is 7.276 ns
Info: + Shortest clock path from clock "clk" to source register is 3.819 ns
Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 7; CLK Node = 'clk'
Info: 2: + IC(1.738 ns) + CELL(0.918 ns) = 3.819 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2|TriEnableDout'
Info: Total cell delay = 2.081 ns ( 54.49 % )
Info: Total interconnect delay = 1.738 ns ( 45.51 % )
Info: + Micro clock to output delay of source is 0.376 ns
Info: + Shortest register to pin delay is 3.081 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y10_N5; Fanout = 8; REG Node = 'USB_T:inst2|TriEnableDout'
Info: 2: + IC(1.477 ns) + CELL(1.604 ns) = 3.081 ns; Loc. = PIN_140; Fanout = 0; PIN Node = 'USB_data[6]'
Info: Total cell delay = 1.604 ns ( 52.06 % )
Info: Total interconnect delay = 1.477 ns ( 47.94 % )
Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
Info: Allocated 100 megabytes of memory during processing
Info: Processing ended: Tue Jun 10 17:58:43 2008
Info: Elapsed time: 00:00:01
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