usb_t.v

来自「这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序」· Verilog 代码 · 共 89 行

module USB_T (
//Inputs
Clock, 
Reset, 
EnablePassivesController,
TXE_n,
RXF_n,
//Outputs 
USB_WU,
Data2USB,
USB_WR,
TriEnableIn,
TriEnableDout
);

input Clock; 
input Reset;
input EnablePassivesController;
input TXE_n;
input RXF_n;
output USB_WR;
output USB_WU;
output TriEnableDout;
output TriEnableIn;
output [7:0] Data2USB; 


reg USB_WR;
reg USB_WU;
reg TriEnableDout;
reg TriEnableIn;
reg [7:0] Data2USB;

reg [4:0] State;
reg [2:0] num_clks;


always @(posedge Clock)
begin
	if (!Reset)  //if reset is 0 then we stay in S0.
		begin
		USB_WR = 1'b0;
		USB_WU = 1'b1;
		TriEnableDout = 1'b0;
		TriEnableIn = 1'b0;
		Data2USB = 8'b00000000; 
		State = 5'b00001;
		end
	else //now things get exciting. . .
	//if (EnablePassivesController == 1'b1)
	    
		begin
		TriEnableDout <= 1'b1;
		if(TXE_n == 1'b0)
		begin
		case (State)
			5'b00001:  //s0: Wait for The Director to enable this controller
			  
				begin
				USB_WR <= 1'b1;
				State <= 5'b00010;
				end
			5'b00010:  //State 1  Put the appropriate data on the Fifo data bus
				begin
				State <= 5'b00100;  //s2
				Data2USB <= 77;
				end
			5'b00100:  //State 0 We now have the data to send to the pc on USBData
				begin
				
				USB_WR <= 1'b0;
				State <= 5'b01000;  //s3
                end
			5'b01000: // we need to de-assert USB_WR after > 50ns so we'll wait 
					//five clocks to do so
                begin
                State<=5'b00001;
                end
		endcase
	end 
	end
	/*else
	begin
				TriEnableDout <= 1'b0;
				State<=5'b00001;
				end
				*/
end
endmodule