📄 usbrefdesign.map.smsg
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Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Jun 10 17:58:32 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USBRefDesign -c USBRefDesign
Info: Found 1 design units, including 1 entities, in source file key_down.v
Info: Found entity 1: key_down
Info: Found 1 design units, including 1 entities, in source file USB_T.v
Info: Found entity 1: USB_T
Info: Found 1 design units, including 1 entities, in source file USBRefDesign.bdf
Info: Found entity 1: USBRefDesign
Info: Elaborating entity "USBRefDesign" for the top level hierarchy
Info: Elaborating entity "USB_T" for hierarchy "USB_T:inst2"
Info: Elaborating entity "key_down" for hierarchy "key_down:inst4"
Warning: Using design file lpm_bustri0.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: lpm_bustri0
Info: Elaborating entity "lpm_bustri0" for hierarchy "lpm_bustri0:inst"
Info: Found 1 design units, including 1 entities, in source file d:/altera/70/quartus/libraries/megafunctions/lpm_bustri.tdf
Info: Found entity 1: lpm_bustri
Info: Elaborating entity "lpm_bustri" for hierarchy "lpm_bustri0:inst|lpm_bustri:lpm_bustri_component"
Info: Elaborated megafunction instantiation "lpm_bustri0:inst|lpm_bustri:lpm_bustri_component"
Info: Power-up level of register "USB_T:inst2|USB_WU" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "USB_T:inst2|USB_WU" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
Info: Duplicate register "USB_T:inst2|Data2USB[4]" merged to single register "USB_T:inst2|Data2USB[7]"
Info: Duplicate register "USB_T:inst2|Data2USB[5]" merged to single register "USB_T:inst2|Data2USB[7]"
Info: Duplicate register "USB_T:inst2|Data2USB[1]" merged to single register "USB_T:inst2|Data2USB[7]"
Info: Duplicate register "USB_T:inst2|Data2USB[3]" merged to single register "USB_T:inst2|Data2USB[6]"
Info: Duplicate register "USB_T:inst2|Data2USB[0]" merged to single register "USB_T:inst2|Data2USB[6]"
Info: Duplicate register "USB_T:inst2|Data2USB[2]" merged to single register "USB_T:inst2|Data2USB[6]"
Warning: Reduced register "USB_T:inst2|Data2USB[7]" with stuck data_in port to stuck value GND
Info: State machine "|USBRefDesign|USB_T:inst2|State" contains 4 states
Info: Selected One-Hot state machine encoding method for state machine "|USBRefDesign|USB_T:inst2|State"
Info: Encoding result for state machine "|USBRefDesign|USB_T:inst2|State"
Info: Completed encoding using 4 state bits
Info: Encoded state bit "USB_T:inst2|State.01000"
Info: Encoded state bit "USB_T:inst2|State.00100"
Info: Encoded state bit "USB_T:inst2|State.00010"
Info: Encoded state bit "USB_T:inst2|State.00001"
Info: State "|USBRefDesign|USB_T:inst2|State.00001" uses code string "0000"
Info: State "|USBRefDesign|USB_T:inst2|State.00100" uses code string "0101"
Info: State "|USBRefDesign|USB_T:inst2|State.00010" uses code string "0011"
Info: State "|USBRefDesign|USB_T:inst2|State.01000" uses code string "1001"
Warning: Hierarchy name "DivideClock:inst5" does not exist. It is associated with user assignments.
Warning: Hierarchy name "SRAMInterface:inst36" does not exist. It is associated with user assignments.
Warning: Output pins are stuck at VCC or GND
Warning: Pin "USB_WU" stuck at VCC
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
Info: Register "inst2/State~51" lost all its fanouts during netlist optimizations.
Warning: Design contains 2 input pin(s) that do not drive logic
Warning: No output dependent on input pin "key_in"
Warning: No output dependent on input pin "RXF_n"
Info: Implemented 24 device resources after synthesis - the final resource count might be different
Info: Implemented 5 input pins
Info: Implemented 2 output pins
Info: Implemented 8 bidirectional pins
Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
Info: Allocated 127 megabytes of memory during processing
Info: Processing ended: Tue Jun 10 17:58:33 2008
Info: Elapsed time: 00:00:01
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