usb_t.v.bak

这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序

module USB_T (
//Inputs
Clock, 
Reset, 
EnablePassivesController,
TXE_n,
RXF_n,
//Outputs 
Data2USB,
USB_WR,
TriEnableIn,
TriEnableDout
);

input Clock; 
input Reset;
input EnablePassivesController;
input TXE_n;
input RXF_n;
output USB_WR;
output TriEnableDout;
output TriEnableIn;
output [7:0] Data2USB; 


reg USB_WR;
reg TriEnableDout;
reg TriEnableIn;
reg [7:0] Data2USB;

reg [4:0] State;
reg [2:0] num_clks;


always @(posedge Clock)
begin
	if (!Reset)  //if reset is 0 then we stay in S0.
		begin
		USB_WR = 1'b0;
		TriEnableDout = 1'b0;
		TriEnableIn = 1'b0;
		Data2USB = 8'b00000000; 
		State = 5'b00001;
		end
	else //now things get exciting. . .
		begin
		case (State)
			5'b00001:  //s0: Wait for The Director to enable this controller
			if (EnablePassivesController == 1'b1)  
				begin
				State = 5'b00010;
				end
			else
				begin
				USB_WR = 1'b0;
				TriEnableDout = 1'b0;
				Data2USB = 8'b00000000; 
				State = 5'b00001;
				end	
			5'b00010:  //State 1  Put the appropriate data on the Fifo data bus
				begin
				State = 5'b00100;  //s2
				Data2USB = 8'd97;
				end
			5'b00100:  //State 0 We now have the data to send to the pc on USBData
			if ((RXF_n == 1) && (TXE_n == 1'b0))
				begin
				State = 5'b01000;  //s3
				TriEnableDout = 1'b1;
				end	
			else
				begin
				State = 5'b00100;
				end
			5'b01000: // we need to de-assert USB_WR after > 50ns so we'll wait 
					//five clocks to do so
				if (num_clks == 6)
					begin
					State = 5'b10000;  //s4
					USB_WR = 1'b0;   //strobing USB_WR from high to low writes the data to the USB Mac
					num_clks = 0;
					TriEnableDout = 1'b0;
					end
				else 
					begin
					State = 5'b01000;  //s3
					num_clks = num_clks + 3'd1; 
					USB_WR = 1'b1;
					end
			5'b10000:  
	        begin
			State = 5'b00001;
			end
			default: State = 5'b00001;
		endcase
	end 
end
endmodule