📄 usbrefdesign.fit.smsg
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Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Jun 10 17:58:34 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off USBRefDesign -c USBRefDesign
Info: Selected device EPM1270T144C5 for design "USBRefDesign"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
Info: Device EPM570T144C5 is compatible
Info: Device EPM570T144I5 is compatible
Info: Device EPM1270T144I5 is compatible
Info: Fitter converted 1 user pins into dedicated programming pins
Info: Pin ~DEV_CLRn~ is reserved at location 61
Info: Fitter is using the Classic Timing Analyzer
Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clk" to use Global clock in PIN 18
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 2.835 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X4_Y10; Fanout = 2; REG Node = 'USB_T:inst2|State.01000'
Info: 2: + IC(0.619 ns) + CELL(0.740 ns) = 1.359 ns; Loc. = LAB_X4_Y10; Fanout = 1; COMB Node = 'USB_T:inst2|USB_WR~286'
Info: 3: + IC(0.672 ns) + CELL(0.804 ns) = 2.835 ns; Loc. = LAB_X4_Y10; Fanout = 2; REG Node = 'USB_T:inst2|USB_WR'
Info: Total cell delay = 1.544 ns ( 54.46 % )
Info: Total interconnect delay = 1.291 ns ( 45.54 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
Info: The peak interconnect region extends from location X0_Y0 to location X8_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
Info: Pin USB_WU has VCC driving its datain port
Info: Following groups of pins have the same output enable
Info: Following pins have the same output enable: USB_T:inst2|TriEnableDout
Info: Type bidirectional pin USB_data[7] uses the 3.3-V LVTTL I/O standard
Info: Type bidirectional pin USB_data[5] uses the 3.3-V LVTTL I/O standard
Info: Type bidirectional pin USB_data[3] uses the 3.3-V LVTTL I/O standard
Info: Type bidirectional pin USB_data[1] uses the 3.3-V LVTTL I/O standard
Info: Type bidirectional pin USB_data[6] uses the 3.3-V LVTTL I/O standard
Info: Type bidirectional pin USB_data[4] uses the 3.3-V LVTTL I/O standard
Info: Type bidirectional pin USB_data[2] uses the 3.3-V LVTTL I/O standard
Info: Type bidirectional pin USB_data[0] uses the 3.3-V LVTTL I/O standard
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Allocated 157 megabytes of memory during processing
Info: Processing ended: Tue Jun 10 17:58:36 2008
Info: Elapsed time: 00:00:02
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