smpdmp_net_22.txt

这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序

189: lcd_controller:inst9|lcd_db[5] DFFE         in=7 lcd_controller:inst9|Select~95 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 LCD_DB[5] lcd_controller:inst9|Select~97 lcd_controller:inst9|lcd_db~547 lcd_controller:inst9|lcd_db~550 
190: lcd_controller:inst9|lcd_db[4] DFFE         in=7 lcd_controller:inst9|Select~99 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 LCD_DB[4] lcd_controller:inst9|Select~101 lcd_controller:inst9|lcd_db~551 lcd_controller:inst9|lcd_db~554 
191: lcd_controller:inst9|lcd_db[3] DFFE         in=7 lcd_controller:inst9|Select~103 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 LCD_DB[3] lcd_controller:inst9|Select~105 lcd_controller:inst9|lcd_db~555 lcd_controller:inst9|lcd_db~558 
192: lcd_controller:inst9|lcd_db[2] DFFE         in=7 lcd_controller:inst9|Select~107 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 LCD_DB[2] lcd_controller:inst9|Select~109 lcd_controller:inst9|lcd_db~561 lcd_controller:inst9|lcd_db~559 
193: lcd_controller:inst9|lcd_db[1] DFFE         in=7 lcd_controller:inst9|Select~111 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 LCD_DB[1] lcd_controller:inst9|Select~113 lcd_controller:inst9|lcd_db~564 lcd_controller:inst9|lcd_db~562 
194: lcd_controller:inst9|lcd_db[0] DFFE         in=7 lcd_controller:inst9|Select~115 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 LCD_DB[0] lcd_controller:inst9|Select~117 lcd_controller:inst9|lcd_db~567 lcd_controller:inst9|lcd_db~565 
195: SRAMInterface:inst36|Addr2SRAM[16] DFFE         in=7 SRAMInterface:inst36|Select~110 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[16] SRAMInterface:inst36|Select~111 SRAMInterface:inst36|Select~114 SRAMInterface:inst36|Addr2SRAM~174 SRAMInterface:inst36|add~33 SRAMInterface:inst36|Select~115 
196: SRAMInterface:inst36|Addr2SRAM[15] DFFE         in=7 SRAMInterface:inst36|Select~116 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[15] SRAMInterface:inst36|Select~117 SRAMInterface:inst36|Select~120 SRAMInterface:inst36|Addr2SRAM~175 SRAMInterface:inst36|add~32 SRAMInterface:inst36|Select~121 
197: SRAMInterface:inst36|Addr2SRAM[14] DFFE         in=7 SRAMInterface:inst36|Select~122 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[14] SRAMInterface:inst36|Select~123 SRAMInterface:inst36|Select~126 SRAMInterface:inst36|Addr2SRAM~176 SRAMInterface:inst36|add~31 SRAMInterface:inst36|Select~127 
198: SRAMInterface:inst36|Addr2SRAM[13] DFFE         in=7 SRAMInterface:inst36|Select~128 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[13] SRAMInterface:inst36|Select~129 SRAMInterface:inst36|Select~132 SRAMInterface:inst36|Addr2SRAM~177 SRAMInterface:inst36|add~30 SRAMInterface:inst36|Select~133 
199: SRAMInterface:inst36|Addr2SRAM[12] DFFE         in=7 SRAMInterface:inst36|Select~134 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[12] SRAMInterface:inst36|Select~135 SRAMInterface:inst36|Select~138 SRAMInterface:inst36|Addr2SRAM~178 SRAMInterface:inst36|add~29 SRAMInterface:inst36|Select~139 
200: SRAMInterface:inst36|Addr2SRAM[11] DFFE         in=7 SRAMInterface:inst36|Select~140 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[11] SRAMInterface:inst36|Select~141 SRAMInterface:inst36|Select~144 SRAMInterface:inst36|Addr2SRAM~179 SRAMInterface:inst36|add~28 SRAMInterface:inst36|Select~145 
201: SRAMInterface:inst36|Addr2SRAM[10] DFFE         in=7 SRAMInterface:inst36|Select~146 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[10] SRAMInterface:inst36|Select~147 SRAMInterface:inst36|Select~150 SRAMInterface:inst36|Addr2SRAM~180 SRAMInterface:inst36|add~27 SRAMInterface:inst36|Select~151 
202: SRAMInterface:inst36|Addr2SRAM[9] DFFE         in=7 SRAMInterface:inst36|Select~152 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[9] SRAMInterface:inst36|Select~153 SRAMInterface:inst36|Select~156 SRAMInterface:inst36|Addr2SRAM~181 SRAMInterface:inst36|add~26 SRAMInterface:inst36|Select~157 
203: SRAMInterface:inst36|Addr2SRAM[8] DFFE         in=7 SRAMInterface:inst36|Select~158 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[8] SRAMInterface:inst36|Select~162 SRAMInterface:inst36|Addr2SRAM~182 SRAMInterface:inst36|add~25 SRAMInterface:inst36|Select~163 SRAMInterface:inst36|Select~159 
204: SRAMInterface:inst36|Addr2SRAM[7] DFFE         in=7 SRAMInterface:inst36|Select~164 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~2 SRAMInterface:inst36|reduce_nor~3 SRAMaddress[7] SRAMInterface:inst36|Select~168 SRAMInterface:inst36|Addr2SRAM~183 SRAMInterface:inst36|add~24 SRAMInterface:inst36|Select~169 SRAMInterface:inst36|Select~165 
205: SRAMInterface:inst36|Addr2SRAM[6] DFFE         in=7 SRAMInterface:inst36|Select~170 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~3 SRAMInterface:inst36|reduce_nor~2 SRAMaddress[6] SRAMInterface:inst36|Select~171 SRAMInterface:inst36|Select~174 SRAMInterface:inst36|Addr2SRAM~184 SRAMInterface:inst36|add~23 SRAMInterface:inst36|Select~175 
206: SRAMInterface:inst36|Addr2SRAM[5] DFFE         in=7 SRAMInterface:inst36|Select~176 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~3 SRAMInterface:inst36|reduce_nor~2 SRAMaddress[5] SRAMInterface:inst36|Select~177 SRAMInterface:inst36|Select~180 SRAMInterface:inst36|Addr2SRAM~185 SRAMInterface:inst36|add~22 SRAMInterface:inst36|Select~181 
207: SRAMInterface:inst36|Addr2SRAM[4] DFFE         in=7 SRAMInterface:inst36|Select~182 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~3 SRAMInterface:inst36|reduce_nor~2 SRAMaddress[4] SRAMInterface:inst36|Select~183 SRAMInterface:inst36|Select~186 SRAMInterface:inst36|Addr2SRAM~186 SRAMInterface:inst36|add~21 SRAMInterface:inst36|Select~187 
208: SRAMInterface:inst36|Addr2SRAM[3] DFFE         in=7 SRAMInterface:inst36|Select~188 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~3 SRAMInterface:inst36|reduce_nor~2 SRAMaddress[3] SRAMInterface:inst36|Select~189 SRAMInterface:inst36|Select~192 SRAMInterface:inst36|Addr2SRAM~187 SRAMInterface:inst36|add~20 SRAMInterface:inst36|Select~193 
209: SRAMInterface:inst36|Addr2SRAM[2] DFFE         in=7 SRAMInterface:inst36|Select~194 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~3 SRAMInterface:inst36|reduce_nor~2 SRAMaddress[2] SRAMInterface:inst36|Select~195 SRAMInterface:inst36|Select~198 SRAMInterface:inst36|Addr2SRAM~188 SRAMInterface:inst36|add~19 SRAMInterface:inst36|Select~199 
210: SRAMInterface:inst36|Addr2SRAM[1] DFFE         in=7 SRAMInterface:inst36|Select~200 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~3 SRAMInterface:inst36|reduce_nor~2 SRAMaddress[1] SRAMInterface:inst36|Select~201 SRAMInterface:inst36|Select~204 SRAMInterface:inst36|Addr2SRAM~189 SRAMInterface:inst36|add~18 SRAMInterface:inst36|Select~205 
211: SRAMInterface:inst36|Addr2SRAM[0] DFFE         in=7 SRAMInterface:inst36|Select~206 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=8 SRAMInterface:inst36|reduce_nor~3 SRAMInterface:inst36|reduce_nor~2 SRAMaddress[0] SRAMInterface:inst36|Select~207 SRAMInterface:inst36|Select~210 SRAMInterface:inst36|Addr2SRAM~190 SRAMInterface:inst36|add~17 SRAMInterface:inst36|Select~211 
212: USBDataBus[7]      TRI_BUS      in=2 USB_d[7] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|dout[7]  out=2 USB_d[7] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|din[7] 
213: USBDataBus[6]      TRI_BUS      in=2 USB_d[6] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|dout[6]  out=2 USB_d[6] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|din[6] 
214: USBDataBus[5]      TRI_BUS      in=2 USB_d[5] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|dout[5]  out=2 USB_d[5] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|din[5] 
215: USBDataBus[4]      TRI_BUS      in=2 USB_d[4] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|dout[4]  out=2 USB_d[4] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|din[4] 
216: USBDataBus[3]      TRI_BUS      in=2 USB_d[3] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|dout[3]  out=2 USB_d[3] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|din[3] 
217: USBDataBus[2]      TRI_BUS      in=2 USB_d[2] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|dout[2]  out=2 USB_d[2] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|din[2] 
218: USBDataBus[1]      TRI_BUS      in=2 USB_d[1] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|dout[1]  out=2 USB_d[1] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|din[1] 
219: USBDataBus[0]      TRI_BUS      in=2 USB_d[0] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|dout[0]  out=2 USB_d[0] USBDataTri:inst7|lpm_bustri:lpm_bustri_component|din[0] 
220: SRAMdata~0         TRI_BUS      in=2 SRAMdata[7] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|dout[7]  out=2 SRAMdata[7] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|din[7] 
221: SRAMdata~1         TRI_BUS      in=2 SRAMdata[6] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|dout[6]  out=2 SRAMdata[6] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|din[6] 
222: SRAMdata~2         TRI_BUS      in=2 SRAMdata[5] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|dout[5]  out=2 SRAMdata[5] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|din[5] 
223: SRAMdata~3         TRI_BUS      in=2 SRAMdata[4] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|dout[4]  out=2 SRAMdata[4] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|din[4] 
224: SRAMdata~4         TRI_BUS      in=2 SRAMdata[3] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|dout[3]  out=2 SRAMdata[3] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|din[3] 
225: SRAMdata~5         TRI_BUS      in=2 SRAMdata[2] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|dout[2]  out=2 SRAMdata[2] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|din[2] 
226: SRAMdata~6         TRI_BUS      in=2 SRAMdata[1] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|dout[1]  out=2 SRAMdata[1] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|din[1] 
227: SRAMdata~7         TRI_BUS      in=2 SRAMdata[0] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|dout[0]  out=2 SRAMdata[0] SRAMDataTri:inst21|lpm_bustri:lpm_bustri_component|din[0] 
228: TempInterface:inst6|MyCounter[23] DFFE         in=7 TempInterface:inst6|Select~57 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 TempInterface:inst6|reduce_nor~1 TempInterface:inst6|reduce_nor~0 TempInterface:inst6|Select~58 TempInterface:inst6|add~45 
229: TempInterface:inst6|MyCounter[22] DFFE         in=7 TempInterface:inst6|Select~62 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 TempInterface:inst6|reduce_nor~0 TempInterface:inst6|reduce_nor~1 TempInterface:inst6|Select~63 TempInterface:inst6|add~44 
230: TempInterface:inst6|MyCounter[21] DFFE         in=7 TempInterface:inst6|Select~67 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 TempInterface:inst6|reduce_nor~1 TempInterface:inst6|reduce_nor~0 TempInterface:inst6|Select~68 TempInterface:inst6|add~43 
231: TempInterface:inst6|MyCounter[20] DFFE         in=7 TempInterface:inst6|Select~72 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 TempInterface:inst6|reduce_nor~0 TempInterface:inst6|reduce_nor~1 TempInterface:inst6|Select~73 TempInterface:inst6|add~42 
232: TempInterface:inst6|MyCounter[19] DFFE         in=7 TempInterface:inst6|Select~77 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 TempInterface:inst6|reduce_nor~0 TempInterface:inst6|reduce_nor~1 TempInterface:inst6|Select~78 TempInterface:inst6|add~41 
233: TempInterface:inst6|MyCounter[18] DFFE         in=7 TempInterface:inst6|Select~82 DivideClock:inst5|HalfClock GND GND VCC VCC GND  out=4 TempInterface:inst6|reduce_nor~0 TempInterface:inst6|reduce_nor~1 TempInterface:inst6|Select~83 TempInterface:inst6|add~40