usbrefdesign.map.qmsg

这是一个在MAX II CPLD利用FT245BM 模块实现USB传输的读写程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 09 13:17:15 2008 " "Info: Processing started: Mon Jun 09 13:17:15 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off USBRefDesign -c USBRefDesign " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off USBRefDesign -c USBRefDesign" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "USBRefDesign.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file USBRefDesign.v" { { "Info" "ISGN_ENTITY_NAME" "1 USBRefDesign " "Info: Found entity 1: USBRefDesign" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "USBRefDesign " "Info: Elaborating entity \"USBRefDesign\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|USBRefDesign\|TX_state 4 " "Info: State machine \"\|USBRefDesign\|TX_state\" contains 4 states" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "One-Hot \|USBRefDesign\|TX_state " "Info: Selected One-Hot state machine encoding method for state machine \"\|USBRefDesign\|TX_state\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|USBRefDesign\|TX_state " "Info: Encoding result for state machine \"\|USBRefDesign\|TX_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "TX_state.TX_state1 " "Info: Encoded state bit \"TX_state.TX_state1\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "TX_state.TX_state3 " "Info: Encoded state bit \"TX_state.TX_state3\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "TX_state.TX_state2 " "Info: Encoded state bit \"TX_state.TX_state2\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "TX_state.TX_state0 " "Info: Encoded state bit \"TX_state.TX_state0\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|USBRefDesign\|TX_state.TX_state0 0000 " "Info: State \"\|USBRefDesign\|TX_state.TX_state0\" uses code string \"0000\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|USBRefDesign\|TX_state.TX_state2 0011 " "Info: State \"\|USBRefDesign\|TX_state.TX_state2\" uses code string \"0011\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|USBRefDesign\|TX_state.TX_state3 0101 " "Info: State \"\|USBRefDesign\|TX_state.TX_state3\" uses code string \"0101\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|USBRefDesign\|TX_state.TX_state1 1001 " "Info: State \"\|USBRefDesign\|TX_state.TX_state1\" uses code string \"1001\"" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 27 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "DivideClock:inst5 " "Warning: Hierarchy name \"DivideClock:inst5\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WSGN_MISSING_HIER_NAME" "SRAMInterface:inst36 " "Warning: Hierarchy name \"SRAMInterface:inst36\" does not exist.  It is associated with user assignments." {  } {  } 0 0 "Hierarchy name \"%1!s!\" does not exist.  It is associated with user assignments." 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "USB_SI VCC " "Warning: Pin \"USB_SI\" stuck at VCC" {  } { { "USBRefDesign.v" "" { Text "F:/ylc627/QuartusProject/USBRefDesign.v" 8 -1 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2 2 " "Info: 2 registers lost all their fanouts during netlist optimizations. The first 2 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "TX_state~21 " "Info: Register \"TX_state~21\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "TX_state~22 " "Info: Register \"TX_state~22\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "35 " "Info: Implemented 35 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "15 " "Info: Implemented 15 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "124 " "Info: Allocated 124 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 09 13:17:17 2008 " "Info: Processing ended: Mon Jun 09 13:17:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}